I have a problem accessing a codec via spi.
If I use the spi_master port descriptor, it works fine.
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on tile[0]: spi_master_interface spi_m_if =
{
XS1_CLKBLK_4,
XS1_CLKBLK_5,
PORT_SPI_MOSI,
PORT_SPI_CLK,
PORT_SPI_MISO
};
on tile[0]: out port SS2 = PORT_SDATA_IN3; // SPI CS8416
void spi_master_init( int spi_clock_div)
{
configure_clock_rate(spi_m_if.blk1, 100, spi_clock_div);
set_port_no_inv(spi_m_if.sclk);
configure_out_port(spi_m_if.sclk, spi_m_if.blk1, 1);
sclk_val = 0xAA;
configure_clock_src(spi_m_if.blk2, spi_m_if.sclk);
configure_out_port(spi_m_if.mosi, spi_m_if.blk2, 0);
configure_in_port(spi_m_if.miso, spi_m_if.blk2);
clearbuf(spi_m_if.mosi);
clearbuf(spi_m_if.sclk);
start_clock(spi_m_if.blk1);
start_clock(spi_m_if.blk2);
}
static inline void spi_master_out_byte_internal( unsigned char data)
{
// MSb-first bit order - SPI standard
unsigned x = bitrev(data) >> 24;
spi_m_if.mosi <: x;
spi_m_if.sclk <: sclk_val;
spi_m_if.sclk <: sclk_val;
sync(spi_m_if.sclk);
spi_m_if.miso :> void;
}
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SPI.spiMISO :> void;
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on tile[0]: fl_SPIPorts SPI =
{
PORT_SPI_MISO,
PORT_SPI_SS,
PORT_SPI_CLK,
PORT_SPI_MOSI,
XS1_CLKBLK_4
};
on tile[0]: clock b_clkblk2 = XS1_CLKBLK_5;
on tile[0]: out port SS2 = PORT_SDATA_IN3; // SPI CS8416
void spi_master_init( int spi_clock_div)
{
// configure ports and clock blocks
configure_clock_rate(SPI.spiClkblk, 100, spi_clock_div);
set_port_no_inv(SPI.spiCLK);
configure_out_port(SPI.spiCLK, SPI.spiClkblk, 1);
sclk_val = 0xAA;
configure_clock_src(b_clkblk2, SPI.spiCLK);
configure_out_port(SPI.spiMOSI, b_clkblk2, 0);
configure_in_port(SPI.spiMISO, b_clkblk2);
clearbuf(SPI.spiMOSI);
clearbuf(SPI.spiCLK);
start_clock(SPI.spiClkblk);
start_clock(b_clkblk2);
}
static inline void spi_master_out_byte_internal( unsigned char data)
{
// MSb-first bit order - SPI standard
unsigned x = bitrev(data) >> 24;
SPI.spiMOSI <: x;
SPI.spiCLK <: sclk_val;
SPI.spiCLK <: sclk_val;
sync(SPI.spiCLK);
SPI.spiMISO :> void; // EXECUTION STOPS HERE
}
regards,
Ck