Overview: The THS-1206 is a 12'b high speed data acquisition device made by Texas Instruments. I am using the XS1-U16A-128 to communicate with the device and process the incoming data.
- Device XS1-U16A-128
- THS-1206 ADC
I have successfully programmed the configuration into the ADC and verified both the timing and ADC response (after configuration) with an oscilloscope. Upon successfully configuring the device, I start the conversion clock (CONVST_CLK). The ADC starts acquiring data and sets the DATA_AV flag when the FIFO has reached the trigger level set during configuration.
Once the DATA_AV flag is set, data may be read by toggling the !RD bit. The issue that I am running into is that I cannot start a read event after the DATA_AV bit is asserted. I can clearly see when the DATA_AV pin is asserted on the oscilloscope. However, I can not start the RD_CLK. It appears to skip this block of code and move on. I have also unsuccessfully tried a variant where I manually toggled the N_RD pin. In this case:
Code: Select all
while(1)
{
select{
case DATA_AV when pinsneq(0):> void:
N_RD<:0;
Delay(1);
N_RD<:1;
break;
case HS_ADC when pinsneq(1):> void:
WR <:1;
start_clock(CONVST_CLK);
break;
}
}
I would really appreciate any and all insight that people may have on this topic. I have hunted on the forums for similar issues to no avail. If it helps I can definitely include a snapshot of the oscilloscope capture to show the problem.
--Thanks!
Kyle
Code: Select all
void GET_HS_ADC_PACKET(streaming chanend c)
{
//This function will initialize the high speed adc on startup and acquire data when the DATA_AV pin is active.
configure_clock_rate(CONVST_CLK, 100, 50);
configure_port_clock_output(HS_ADC_TRIGGER, CONVST_CLK);
configure_clock_rate(RD_CLK, 100, 5);
configure_port_clock_output(N_RD, RD_CLK);
N_RD <: 1; //RD input has to be tied to high-level when using R/!W, !CS0-controlled.
WR <: 0; //WR input is tied low while writing to the ADC
CS1 <: 1; //CS1 input is tied high to set ADC to enable Data_I/O
N_CS0 <: 0; //N_CS0 input is always 0.
// Configure the THS1206 ADC. Two writes sequences are required:
HS_ADC <: RST_ADC; //RESET ADC
HS_ADC <: CLR_RST_ADC; //Clear ADC RESET
HS_ADC <: CNTRL_REG0; //Set control register 0: Need to implement hs_adc_config_reg0 structs later...
HS_ADC <: CNTRL_REG1; //Set control register 1: Need to implement hs_adc_config_reg1 structs later...
HS_ADC <: RST_ADC; //RESET ADC
HS_ADC <: CLR_RST_ADC; //Clear ADC RESET
HS_ADC <: CNTRL_REG0; //Set control register 0: Need to implement hs_adc_config_reg0 structs later...
HS_ADC <: CNTRL_REG1; //Set control register 1: Need to implement hs_adc_config_reg1 structs later...
HS_ADC :> void;
//Use hardware trigger to start acquiring data.
select{
case HS_ADC when pinsneq(1):> void:
WR <:1;
start_clock(CONVST_CLK);
break;
}
//Use hardware trigger to start reading data.
select{
case DATA_AV when pinseq(1):> void:
start_clock(RD_CLK);
break;
}
select{
case DATA_AV when pinsneq(1) :> void:
stop_clock(RD_CLK);
break;
}
