Hi again,
I made some progress using the ADAT library and can read the sample array and hand it over to the i2s in frame_master to send it out. I hear audio but clicking and drops - I guess it's because the entire system runs on the PL611 to make the DACs happy (indeed the gpio are set accordingly) but now I want to slave to the incoming ADAT/SPDIF clock. The adat_rx library is free-flying and doesn't need a clock and I don't want to introduce an ASRC. I tried to set the gpio_output to select the CS2100 but then no master clock is generated and I wonder how to feed the PLL with my digital audio bitstream (is this done in hardware?). I also read about the clockgen but couldn't find an example on how to gain the clock and then: where to go with it? I'm on the xCore-200 MC board.
Can somebody please explain clocking/PLL in combination with digital input and without ASRC, the documentation isn't really helpful to me, it seems.
Thanks a lot!
sync clock to digital in - how to PLL?
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Hi,
in UAC2 mode there is CLOCK_UNIT in USB audio topology, so you can change clocking mode Internal/Digital IN via Thesycon USB Audio 2.0 driver & TUSBAudioCplApp.exe.
In UAC1 mode there isn't CLOCK_UNIT. clockGen() in clockgen.xc can generate clock from internal generator or extract clock from input digital stream. You can switch mode changing clkMode in code.
By default clkMode = CLOCK_INTERNAL and I got glitches in audio every 8,5 sec when tried to sync to S/PDIF input. When I change clkMode to CLOCK_SPDIF audio becomes glithes free.
On my board clockGen outputs clock to PLL CS2300, PLL generates MCLK and outputs it to all board.
in UAC2 mode there is CLOCK_UNIT in USB audio topology, so you can change clocking mode Internal/Digital IN via Thesycon USB Audio 2.0 driver & TUSBAudioCplApp.exe.
In UAC1 mode there isn't CLOCK_UNIT. clockGen() in clockgen.xc can generate clock from internal generator or extract clock from input digital stream. You can switch mode changing clkMode in code.
By default clkMode = CLOCK_INTERNAL and I got glitches in audio every 8,5 sec when tried to sync to S/PDIF input. When I change clkMode to CLOCK_SPDIF audio becomes glithes free.
On my board clockGen outputs clock to PLL CS2300, PLL generates MCLK and outputs it to all board.
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- Joined: Wed Feb 04, 2015 11:41 pm
Thanks. I'm not using the USB library. I take the samples from the adat_rx and send it to the I2S and want to clock to the digital in. Can I use the clockgen also for this?
Thanks.
Thanks.