Confusion about Master Clock generation in app_usb_aud_xk_316_mc Topic is solved

[satov]

Hello! I'm new here and I'm trying to understand the fundamentals of USB audio on XMOS. I'm using the XK-AUDIO-316-MC-AB with the default app app_usb_aud_xk_316_mc that comes with sw_usb_audio-_sw_9_0_0. My build configuration is as simple as 2AMi2o2xxxxxx, which should be the most vanilla USB-I2S bridge.

I understand that in USB asynchronous synchronization mode (our situation here), the XMOS generates a MCLK that is the reference time of the whole USB/I2S audio stack (I may be abusing terminology here). The PC uses the timing information sent on the feedback endpoint (the timing info is generated by XMOS using the MCLK as reference) to generate the right amount of samples that prevents under/overflows. The same MCLK is used by lib_i2s to generates BCLK, LRCLK, etc. Is this correct so far?

Now, the MCLK in XK-AUDIO-316-MC-AB can be generated in three ways: CS2100, SI5351A, and using the secondary PLL internal to the XU316-1024-TQ128. By looking at the xk_audio_316_mc_ab_config_t struct in sw_usb_audio-_sw_9_0_0\sw_usb_audio\app_usb_aud_xk_316_mc_minimal\src\extensions\audiohw.xc the clk_mode is set to CLK_FIXED (because it's USB asynchronous mode) and the xk_audio_316_mc_ab_board_setup function in xk_audio_316_mc_ab_board.xc sets bit 7 of PORT_CTRL to 1, which means that the MCLK_SOURCE is the XU316 secondary PLL.

By looking at the schematic of the board, U27 is disabled, so the signal MCLK_XMOS is routed to MCLK_ADC/DAC/DIG by U25 and U23. Additionally the line MCLK_XMOS goes to pins X1D11 and X0D11 of the XU316.

By looking at the datasheet of the chip (section 7.2), I read "When used as an application clock, the output [of the secondary PLL] is routed to pin X1D11 and port 1D on core 1" (should it say tile 1 instead of core 1???). If I go back to the schematic I understand the the MCLK_XMOS signal comes OUT of X1D11 and goes IN X0D11. I understand that it is routed back to X0D11 such that timing information for the feedback endpoint can be generated by the code running on tile0. The datasheet also says "When enabled, tile 1 can input the clock on port 1D."

Port connected to pin X1D11 on tile 1 is called PORT_MCLK_IN in xk-audio-316-mc.xn.
Port connected to pin X0D11 on tile 0 is called PORT_MCLK_IN_USB in xk-audio-316-mc.xn.

Now, what confuses me is that both ports are configured as input ports in lib_xua\src\core\main.xc, while I would expect PORT_MCLK_IN to be an output since it's where the XU316 outputs the MCLK generated by its secondary PLL.

Could you please clarify?
Thanks

[Joe]

Hi,

All sounds correct to me.

The ports are not the same as the pins.

Port 1D is defined as an input and gets its signal from the X1D11 pin. The X1D11 pin is set up as an output by the SS_APP_CLK_DIVIDER register and outputs the clock from the appPLL.

See definition of this register in the datasheet.

Bit 16 is defined as: "Application clock divider disable. When set to 0, the divider is enabled, and pin X1D11 will be connected to the application clock rather than to port 1D."

So we use that to drive an output on X1D11 while simultaneously inputting that clock to port 1D.

Hope that clears it up?

Cheers,
Joe

[satov]

Ok, thanks.

So the MCLK (secondary PLL) is output on pin X1D11 (I see that xk_audio_316_mc_ab_AudioHwInit calls sw_pll_fixed_clock to do that by writing the register you mentioned), so that it can be routed via PCB to X0D11 for the feedback-endpoint. Then, on tile1, XS1_PORT_1D is called PORT_MCLK_IN and that is an input, it takes what comes out of X1D11 so that the XUA_AudioHub task can use it as MCLK for the I2S master, correct?

[Joe]

That's correct.