sliceKIT is here!
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I must admit I agree with Heater on this. Marketing double speak has spoilt the sliceKIT introduction for me. It's not a 16-core device, please correct this marketing double speak
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About the critics in Terminology, i would like to say :
how you speak of something is not very important .
Only the facts are important.
The L2-C5 chip is a 500Mhz or a 1Ghz dual core ?
how you speak of something is not very important .
Only the facts are important.
The L2-C5 chip is a 500Mhz or a 1Ghz dual core ?
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How you speak of something is _very_ important. Taking well-established
vernacular and using the words to mean something else entirely is a
politicians' game. Engineers (like most of us here are: tinkerers are
engineers as well) hate it, a) because we do not like politicians (and
management :-) ) in the first place; and b) we need to use those words
to get our job done, and for that, those words need to have a clear,
unambiguous meaning.
Calling a thread a logical core is one thing; we could call them "bunnies"
and it wouldn't change a thing (after re-educating everyone, and probably
some trademark lawsuits).
But calling it a "core" just causes chaos (because until three days ago
core meant something else entirely). And people feel cheated because
it is (or at least, seems to be) such an obvious attempt at looking better
than it actually is.
vernacular and using the words to mean something else entirely is a
politicians' game. Engineers (like most of us here are: tinkerers are
engineers as well) hate it, a) because we do not like politicians (and
management :-) ) in the first place; and b) we need to use those words
to get our job done, and for that, those words need to have a clear,
unambiguous meaning.
Calling a thread a logical core is one thing; we could call them "bunnies"
and it wouldn't change a thing (after re-educating everyone, and probably
some trademark lawsuits).
But calling it a "core" just causes chaos (because until three days ago
core meant something else entirely). And people feel cheated because
it is (or at least, seems to be) such an obvious attempt at looking better
than it actually is.
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[emphasis mine, above]segher wrote:How you speak of something is _very_ important. Taking well-established vernacular and using the words to mean something else entirely is a politicians' game. Engineers (like most of us here are: tinkerers are engineers as well) hate it, a) because we do not like politicians (and management :-) ) in the first place; and b) we need to use those words to get our job done, and for that, those words need to have a clear, unambiguous meaning.
Calling a thread a logical core is one thing; we could call them "bunnies" and it wouldn't change a thing (after re-educating everyone, and probably some trademark lawsuits).
But calling it a "core" just causes chaos (because until three days ago core meant something else entirely). And people feel cheated because it is (or at least, seems to be) such an obvious attempt at looking better than it actually is.
Couldn't have said it better. I really can't see any other interpretation than this is a deliberate attempt to mislead. You can't just redefine a word to make your product look better ... there's a well-understood word for that, we call it "lying". I feel sufficiently strongly about it that if I were still in the UK I would contact the advertising standards authority (something I've never even contemplated doing before), and I *like* XMOS and their chips.
For me, this smacks of snake oil and it's an embarrassment to the company's good name. As your typical engineer I doubt I'm alone in this; I think the marketing dept. have seriously misjudged their customer base (because it's *engineers* who'll pick the product to use). Frankly, I'm disgusted and although I'll keep on using the XMOS in my current design, I'll think very carefully about supporting such a company in the future.
Simon.
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Yeah they renamed threads to cores now and cores to tiles. This decision was obviusly marketing to make the chips seam more than what they are. I don't like it eater because this is not what a core is. Xmos did start everything from scratch with the website and tools and all but still threads are not cores. This will surely get them more attention around the web tho as everyone will talk about 16 core chips.
In any case this thread is about the slicekit rather than the new naming conventions.
In my opinion the slicekit is a pretty neat idea since the new addon slices can be added to it later along the new IP for that task. There are still some very basic slices missing like a simple lcd display, memory cards,PS/2,VGA... all of them needing very little design effort. Also surprised there is no USB slice as this is the main market for xmos.
In any case this thread is about the slicekit rather than the new naming conventions.
In my opinion the slicekit is a pretty neat idea since the new addon slices can be added to it later along the new IP for that task. There are still some very basic slices missing like a simple lcd display, memory cards,PS/2,VGA... all of them needing very little design effort. Also surprised there is no USB slice as this is the main market for xmos.
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Yes indeed, let's not taint this thread about this awesome new product withBerni wrote:In any case this thread is about the slicekit rather than the new naming conventions.
our misgivings about the marketing move.
And you can make some yourself, too ;-)In my opinion the slicekit is a pretty neat idea since the new addon slices can be added to it later along the new IP for that task.
All of those are barely more than a connector on a piece of PCB. Maybe thereThere are still some very basic slices missing like a simple lcd display, memory cards,PS/2,VGA... all of them needing very little design effort.
should be a kit with many of those, and some breakout boards perhaps. Or
XMOS is expecting us to make those ourselves.
Right, I noticed that as well. A USB slice would be an L1 + ULPI; but for theAlso surprised there is no USB slice as this is the main market for xmos.
resulting system to be closer to what you would create as standalone system,
the USB should really be on the L2 on the baseboard (which then means you
lose a lot of I/O on it, probably limited to two slices). USB sucks :-P
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I think there is no USB slice, because the USB Audio 2.0 DJ Kit (check the current picture) looks more or less like another sliceKit core board plus the Audio slice, but with the new SU1.
Hopefully they will finally introduce the 700Mhz version together with the release of that board.
I like the sliceKit, too. The only strange thing seems that xConnectSliceJTAG2 (;-)) adapter board.
Will there be a xJTAG3 (based on the SU1?) with PCIe connector?
Oh and a "me too" for absolutely changing the kit advertisements. At least to "16 _logical_ cores".
Hopefully they will finally introduce the 700Mhz version together with the release of that board.
I like the sliceKit, too. The only strange thing seems that xConnectSliceJTAG2 (;-)) adapter board.
Will there be a xJTAG3 (based on the SU1?) with PCIe connector?
Oh and a "me too" for absolutely changing the kit advertisements. At least to "16 _logical_ cores".
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I sure hope not! The whole point of having a standardised debugozel wrote:The only strange thing seems that xConnectSliceJTAG2 (;-)) adapter board.
Will there be a xJTAG3 (based on the SU1?) with PCIe connector?
connector is that it is standardised.
You need an adapter board from XSYS to Chain now, that is true;
but the alternative is to also have adapter boards from "Square XSYS"
(for lack of a better name: I mean "PCIe XSYS") to XSYS, or to have
multiple different debug adapters (a "sliceTAG", an "xk1TAG", etc.)
Another issue is that it is much easier to include a footprint for an XSYS
plug on your own custom boards, than it is to route those signals to
PCIe fingers (and then your board has to have the correct thickness too,
and it takes more space and possibly extra cost to manufacture, etc.)
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I can comment a little on this, we are not planning to change the standard XSYS connector to PCIe at this time as stated it is the standard way the tools interface to all development boards and is much simpler to put on customer boards. As for an XTAG-3 or such a product this does make sense using the SU1, the BOM reduction and extra functionality this would allow whilst still being compatible with the 20 pin XSYS connector is something we are definitely looking at.ozel wrote: I like the sliceKit, too. The only strange thing seems that xConnectSliceJTAG2 (;-)) adapter board.
Will there be a xJTAG3 (based on the SU1?) with PCIe connector?
Also the adapter board for the XTAG-2 and the slicekit makes more sense when you see slicekits chained together.
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Yes, that was the problem we faced when deciding whether to make some kind of prototyping board. We couldn't think of enough actually useful things to justify it. There is also a limited prototyping area on the GPIO slice, and if you just need to wire things into a given slot you can solder wires directly to the 20 testpoints each slot has on the coreboard, or header pins can easily be soldered to them.segher wrote: All of those are barely more than a connector on a piece of PCB. Maybe there
should be a kit with many of those, and some breakout boards perhaps. Or
XMOS is expecting us to make those ourselves.
So what features over and above this do you think would be useful?
Yes, ULPI needs two slots unfortunately.Right, I noticed that as well. A USB slice would be an L1 + ULPI; but for the
resulting system to be closer to what you would create as standalone system,
the USB should really be on the L2 on the baseboard (which then means you
lose a lot of I/O on it, probably limited to two slices). USB sucks :-P