I've been trying to figure out the UDP connection using xCORE-200 Explorer Kit. For that, I have started with the UDP example that is for the sliceKIT.
There for sliceKIT we have the ports as,
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port p_eth_rxclk = on tile[1]: XS1_PORT_1J;
port p_eth_rxd = on tile[1]: XS1_PORT_4E;
port p_eth_txd = on tile[1]: XS1_PORT_4F;
port p_eth_rxdv = on tile[1]: XS1_PORT_1K;
port p_eth_txen = on tile[1]: XS1_PORT_1L;
port p_eth_txclk = on tile[1]: XS1_PORT_1I;
port p_eth_int = on tile[1]: XS1_PORT_1O;
port p_eth_rxerr = on tile[1]: XS1_PORT_1P;
port p_eth_timing = on tile[1]: XS1_PORT_8C;
clock eth_rxclk = on tile[1]: XS1_CLKBLK_1;
clock eth_txclk = on tile[1]: XS1_CLKBLK_2;
port p_smi_mdio = on tile[1]: XS1_PORT_1M;
port p_smi_mdc = on tile[1]: XS1_PORT_1N;
MDIO, MDC, TX_EN, and TIMING pins are not given. (Or probably related to other peripherals) Can you please help me adjust these pins for xCORE-200 Explorer RGMII? Thank you in advance . Below, you 'll find my current version, but with several ambiguities.
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port p_eth_rxclk = on tile[1]: XS1_PORT_1O;
port p_eth_rxd = on tile[1]: XS1_PORT_8A;//4E
port p_eth_txd = on tile[1]: XS1_PORT_8B;
port p_eth_rxdv = on tile[1]: XS1_PORT_1B;
port p_eth_txen = on tile[1]: XS1_PORT_1L; //?
port p_eth_txclk = on tile[1]: XS1_PORT_1G;
port p_eth_int = on tile[1]: XS1_PORT_1O; //?
port p_eth_rxerr = on tile[1]: XS1_PORT_1A;
port p_eth_timing = on tile[1]: XS1_PORT_8C; //?
clock eth_rxclk = on tile[1]: XS1_CLKBLK_1; //?
clock eth_txclk = on tile[1]: XS1_CLKBLK_2; //?
port p_smi_mdio = on tile[1]: XS1_PORT_1M; //?
port p_smi_mdc = on tile[1]: XS1_PORT_1N; //?