First, I modify the spdif receive module into I2S master. By using the xscope tool, I have traced the sample at the trace window, the I2S master moduel works fine.
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on tile[AUDIO_TILE]: {
configure_clock_src(R18_XMOS_MCLK, R18_MCLK);
start_clock(R18_XMOS_MCLK);
i2s_master(R18_xmos_i2s, R18_data_out, 1, R18_data_in, 1, R18_BCLK, R18_LRCLK, R18_XMOS_BCLK, R18_XMOS_MCLK);
}
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void R18_to_xmos(server i2s_callback_if i2s, client serial_transfer_push_if i_serial_in)
{
while(1){
select{
case i2s.init(i2s_config_t &?i2s_config, tdm_config_t &?tdm_config):
i2s_config.mode = I2S_MODE_I2S;
i2s_config.mclk_bclk_ratio = 8;//11.2896MHz or 2.8224MHz
delay_milliseconds(2);
// debug_printf("this is a test*********\n");
break;
case i2s.restart_check() -> i2s_restart_t restart:
// This application never restarts the I2S bus
restart = I2S_NO_RESTART;
break;
case i2s.receive(size_t index, int32_t sample):
//in_samps[index] = sample;
i_serial_in.push(sample, index);
//zhengyang
xscope_int(R18_LEFT, sample);
break;
case i2s.send(size_t index) -> int32_t sample:
break;
}
}
}
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on tile[USB_TILE]: {
debug_printf("Starting I2S\n");
i2s_slave(xmos_dsp_i2s, DSP_data_out, 1, DSP_data_in, 1, DSP_BCLK, DSP_LRCLK, XMOS_DSP_BCLK);
}
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#define MUTE_MS_AFTER_SR_CHANGE 350 //350ms. Avoids incorrect rate playing momentarily while new rate is detected
//Shim task to handle setup and streaming of I2S samples from block2serial to the I2S module
#pragma unsafe arrays //Performance optimisation of i2s_handler task
void xmos_to_dsp(server i2s_callback_if i2s, client serial_transfer_pull_if i_serial_out)
{
unsigned sample_rate = DEFAULT_FREQ_HZ_I2S;
unsigned mclk_rate;
unsigned restart_status = I2S_NO_RESTART;
unsigned mute_counter; //Non zero indicates mute. Initialised on I2S init SR change
while (1) {
select {
case i2s.init(i2s_config_t &?i2s_config, tdm_config_t &?tdm_config):
if (!(sample_rate % 48000)) mclk_rate = MCLK_FREQUENCY_48; //Initialise MCLK to appropriate multiple of sample_rate
else mclk_rate = MCLK_FREQUENCY_44;
i2s_config.mclk_bclk_ratio = mclk_rate / (sample_rate << 6);
i2s_config.mode = I2S_MODE_I2S;
debug_printf("Initializing I2S to %dHz and MCLK to %dHz\n", sample_rate, mclk_rate);
restart_status = I2S_NO_RESTART;
mute_counter = (sample_rate * MUTE_MS_AFTER_SR_CHANGE) / 1000; //Initialise to a number of milliseconds
break;
//Start of I2S frame
case i2s.restart_check() -> i2s_restart_t ret:
ret = restart_status;
break;
//Get samples from ADC
case i2s.receive(size_t index, int32_t sample):
break;
//Send samples to DAC
case i2s.send(size_t index) -> int32_t sample:
sample = i_serial_out.pull(index);
if (mute_counter){
sample = 0;
mute_counter --;
}
break;
}
}
}
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Initializing I2S to 44100Hz and MCLK to 22579200Hz
Initializing I2S to 44100Hz and MCLK to 22579200Hz
Initializing I2S to 44100Hz and MCLK to 22579200Hz
Initializing I2S to 44100Hz and MCLK to 22579200Hz
Initializing I2S to 44100Hz and MCLK to 22579200Hz
Initializing I2S to 44100Hz and MCLK to 22579200Hz
Initializing I2S to 44100Hz and MCLK to 22579200Hz
Initializing I2S to 44100Hz and MCLK to 22579200Hz
Initializing I2S to 44100Hz and MCLK to 22579200Hz
......
If anyone know the problem, please tell me, thank you very much!
This is the whole test project: