Any idea about future plans?
- Any plan to release a G4 with 128 pin in TQFP (we don't necessarily need all those pins on BGA512) ?
- Any plan to release an L2 in 128 TQFP ?
- Any plan to release an L1/128 or L1/64 with 256 or 512KB of RAM ?
XS1-L1-48TQFP
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I'd be interested in a TQFP-144 of that G4 part, a pad below the package to transmit heat is also ok. The >64kbytes versions are also more than welcome !!!.
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The link C is used, as when in ULPI (USB) mode, these pins are still available on the 32bit port. This is hardware design checklist refers to the signals (ports) rather than XMOS-links. In ULPI mode the XMOS-Link A is available, but the 4/8/16bit port using these signals is not.
For pricing please see Digi-Key - they should be listed on their website soon.
Thanks for the info on the DEBUG_N pin - I'll get it fixed in the datasheet. It is a typo, rather than a pinout error. DEBUG_N is not present on the XS1-L1-48TQFP. The DEBUG_N pin does not need to be wired on single core designs. It is used to stop multi-core skidding when the multi-processor designs are stopped for debug (so they are all stop at the same instruction - the JTAG chain is not that quick at stopping everything). If the DEBUG_N is not wired then (currently) the only issue is that your likely to get more skidding.
Kind Regards,
Corin
For pricing please see Digi-Key - they should be listed on their website soon.
Thanks for the info on the DEBUG_N pin - I'll get it fixed in the datasheet. It is a typo, rather than a pinout error. DEBUG_N is not present on the XS1-L1-48TQFP. The DEBUG_N pin does not need to be wired on single core designs. It is used to stop multi-core skidding when the multi-processor designs are stopped for debug (so they are all stop at the same instruction - the JTAG chain is not that quick at stopping everything). If the DEBUG_N is not wired then (currently) the only issue is that your likely to get more skidding.
Kind Regards,
Corin
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To octal & ale500,
We have no plans at this time to release the G4 or L2 devices in other packages, and with our current generation products the SRAM limit is 64KB per XCore, as this is monolithic to the die on the chip.
Thank you for your comments, we are always interested in feedback from customers, as it helps us to develop new products / packages where there is strong interest and commercial opportunity.
Kind Regards,
Corin
We have no plans at this time to release the G4 or L2 devices in other packages, and with our current generation products the SRAM limit is 64KB per XCore, as this is monolithic to the die on the chip.
Thank you for your comments, we are always interested in feedback from customers, as it helps us to develop new products / packages where there is strong interest and commercial opportunity.
Kind Regards,
Corin
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Well... I think we will have to wait till the next iteration for more memory :)... I see the packages as less likely.
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The XS-L!-48TQFP is now available on Digikey:
http://search.digikey.com/scripts/DkSea ... -L01A-TQ48
Product information on XMOS web site: http://www.xmos.com/products/xs1-l-family/l1tq48
Joerg
http://search.digikey.com/scripts/DkSea ... -L01A-TQ48
Product information on XMOS web site: http://www.xmos.com/products/xs1-l-family/l1tq48
Joerg
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I saw it... but I wanted more and more accessible pins and not less... but I'm glad the XMOS family is growing !!
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It's not actually available, though, they show zero stock.
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I think this is an excellent package. I've just made a design using it. We use it to replace another MCU in a 48 pin package. I welcome all the single-bit ports -- we push a lot of data around serially, so those come in very handy.ale500 wrote:I saw it... but I wanted more and more accessible pins and not less... but I'm glad the XMOS family is growing !!