To try and do this, I have two clock blocks. One is driven by MCLK which clocks a buffered output (call this output bclk). I loop bclk around from the output pin to an input pin (and also to the DAC), and that drives the second clock block. That block is the clock for the buffered data output, dac_data.
On every edge of the word clock (LRCK) I then output 0xCCCCCCCC to the bclk output (effectively outputting a square wave at MCLK/4, or 64*Fs, and then output the data to the dac_data register, which should be clocked out
by bclk. Instead, if I do the output to dac_data everything seems to stall; if I don't I at least get the clock output. My code looks like:
Code: Select all
on stdcore[2]: out buffered port:32 dac_data = DAC_DATA;
on stdcore[2]: out buffered port:32 dac_bclk_out = DAC_BCLK_OUT;
on stdcore[2]: in port dac_mclk = DAC_MCLK;
on stdcore[2]: in port dac_bclk_in = DAC_BCLK_IN;
on stdcore[2]: clock clk1 = XS1_CLKBLK_1;
on stdcore[2]: clock clk2 = XS1_CLKBLK_2;
on stdcore[2]: in port dac_lrck = DAC_LRCK;
void dac(void)
{
int lr = 0;
int r_data;
configure_clock_src(clk1, dac_mclk);
configure_out_port(dac_bclk_out, clk1, 0);
configure_clock_src(clk2, dac_bclk_in);
configure_out_port(dac_data, clk2, 0);
start_clock(clk1);
start_clock(clk2);
while(1)
{
dac_lrck when pinsneq(lr) :> lr;
dac_bclk_out <: 0xCCCCCCCC;
dac_data:24 <: r_data;
dac_bclk_out:16 <: 0xCCCCCCCC;
}
}
Paul