FIR Filter specified speed using sc_dsp_filters

[bearcat]

I was reviewing the speed for a FIR filter as listed in the "DSP Performance on XL-1 Device" from XMOS in detail. It says on page 5: 100 tap FIR filter, 150kHz using 50Mips. It lists using the sc_dsp_filters on github.

If my calculations are correct, that would be 3.3 XMOS instruction cycles per tap. I have reviewed the code from sc_dsp_filters in the XTA timing analyzer, and am seeing 5 cycles (with no FNOP's) for the firASM_DoubleData_SingleThread.S program. The other fir XC routine in there looks 5+.

I have achieved about 4.5 instruction cycles per tap, but 3.3 looks unachievable.

Am I looking at the wrong code? Or can someone point out my error, or point me in the right direction how to achieve these speeds?