My "Application" is still in its infancy, and it has a bunch of teething problems.
I've got the slicekit with the ether slice in the circle port. There is one process that generates packets, and another one that is supposed to receive them (via loopback cable).
Sadly, whatever I receive is not what I have sent. I send 37 U32 (unsigned 32-bit words) and I receive a lot less (28-29 U32)
At first, I compared the TXEN and the RXDV signals on the oscilloscope, and they looked ok.
Then I toggled a gpio port bin whenever I wrote to the TX_Data and it looked fine (320ns/32Bits).
But when I toggled another gpio port pin whenever I read an U32 from the RX_Data, I saw something odd: It took about 400ns/32Bits to read! RX_Clock was fine with 25MHz.
My receiver code looks like this:
1. Definition of the port structure:
Code: Select all
typedef struct MII_Receive_t {
in buffered port:32 RX_Data;
in port RX_DataValid;
in port RX_ClockPort;
in port RX_Error;
clock RX_Clock;
}MII_Receive_t;
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on stdcore[1]: MII_Receive_t Downlink_RX = {
XS1_PORT_4E, XS1_PORT_1K, XS1_PORT_1J, XS1_PORT_1P, XS1_CLKBLK_1
};
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void ConfigReceive( MII_Receive_t &Port )
{
configure_clock_src( Port.RX_Clock, Port.RX_ClockPort );
configure_in_port( Port.RX_Data, Port.RX_Clock );
configure_in_port( Port.RX_DataValid, Port.RX_Clock );
configure_in_port_strobed_slave( Port.RX_Data, Port.RX_DataValid, Port.RX_Clock );
start_clock( Port.RX_Clock );
}
Code: Select all
on stdcore[1]: out port DebugBits = XS1_PORT_4B;
#define DBG_MAXBUF (40)
void DownlinkReceiver( MII_Receive_t &Port, chanend PacketTarget, chanend AudioTarget, chanend CommandTarget )
{
unsigned DBG_Count;
unsigned DBG_Count2;
unsigned DBG_Buf[DBG_MAXBUF];
unsigned PacketData;
unsigned PacketValid;
// If there is a packet currently in the pipe, wait it out.
Port.RX_DataValid when pinseq(0) :> void;
while(1){
// As per book, wait for DataValid
Port.RX_DataValid when pinsneq(0) :> PacketValid;
// Wait for End-of-preamble
Port.RX_Data when pinseq(0x0D) :> void;
DBG_Count2 = DBG_Count;
DBG_Count = 0;
do{
select{
case Port.RX_Data :> PacketData:
// A longword should have come here...
// Store whatever we got
if (DBG_Count<DBG_MAXBUF) DBG_Buf[DBG_Count] = PacketData;
DBG_Count++;
// Toggle Bit
DebugBits <: DBG_Count;
break;
case Port.RX_DataValid when pinseq(0) :> PacketValid:
// Packet ends.
break;
}
} while( PacketValid );
}
}
EDIT: The received packet is stored in DBG_Buf[], and it shows absolutely no resembly of the original packet. Added some comments.
Any help is appreciated.
Yours, Christian Treczoks