About Tiles, Nodes, and Switches

[JPSohl]

Is a Tile the same thing as a Digital Node? If not, is a Switch part of a Tile or not?I believe the following three items to be true:1) A Tile is a set of 4, 5, 6, or 8 logical cores with 64 K of memory and items associated with the set of cores (Channel Ends, Clock Blocks, Locks, xTIME, PLL, etc).2) A Digital Node consists of a Tile plus a Switch. 3) an XS1-U16A contains TWO Digital Nodes and ONE Analog Node. Can someone confirm these suppositions?The documentation is very muddled.1) The new “XCore Architecture Flier” (2014/5/30), which I like very much, says in the first paragraph of page 2 “Each xCORE device has one or more tiles. Each tile has up to eight independent 32-bit logical cores that run in parallel without interruption from other cores. A tile also includes the xTIME scheduler, the xCONNECT switch, ports and SRAM.” This clearly states that a switch is inside a tile.The diagram on page 3 of the same flier shows a two-tile chip with a single switch floating between them. I thought there was one switch per tile. I also thought that a XCONNECT link between tile[0] and tile[1] would have to go tile0 – switch0 – switch1 – tile1. 2) The “xCONNECT Architecture” (2013/11/13), has a very helpful hand-drawn diagram on page 1, which shows that the Switch is inside the Tile. Page 5 of the same document says “The xCORE tile in the XS1-L is connected to the switch by four internal links, . . .” which implies that the switch is separate from the tile. 3) The XS1-U16A datasheet (2014/3/25) says on page 11 section 6: Product Overview “The XS1-U16A-128-FB217 comprises a digital and an analog node, as shown in Figure 3.” Figure 3 then shows TWO tiles and an analog node. Does this mean that the Digital Node comprises two Tiles? Or should it say that there are TWO digital nodes and an analog node? “The digital node comprises an xCORE Tile, a Switch, and a PLL (Phase-locked-loop).” The last sentence implies that an xCORE Tile is separate from a Switch. Furthermore, Appendix P “xCORE Tile Configuration” and Appendix O “Digital Node Configuration” implies that Tiles are not identical to Digital Nodes. Some clarity would help.

[Bianco]

If you look at the older XS1-G architecture, there is one switch that connects to 2-4 tiles. One could conclude from this that a switch is essentially not part of a tile. The XS1-L series (and the U/A) has a switch for each tile but this is just an implementation choice. If you design a single tile chip, you would like to have a switch too. A node should be seen as the switch with its connected "devices", this could be tiles, but also more specific circuitry like the ADC in the analog node.