I forgot about it. I came across one of the little PCBs I designed the other day with one of the chips mounted on it, I ought to resurrect the project. I've got several of the PCBs, if anyone wants one.
So did you get any MHz numbers on this ?
From my other thread, it seems you cannot easily gate clocks (ie so clk edges match data bits), but I see these data sheet specs on QuadSPI parts Tsu/Th on the CSn and Data lines.Winbond (104MHz) Tsu CS =5ns Th CS = 5ns Tsu D= 1.5ns Th D = 4ns Tdo = 5ns
Atmel (100MHz) Tsu CS =5ns Th CS = 5ns Tsu D= 2ns Th D = 1ns Tdo = 5ns
These are all relative to the same clock edge, and active read edge is always _/=
The CS is not quite as fast as Di, but it is fast enough to choose the 'right' clock edge at 100MHz
(assumes no skew on outputs of CLK and DATA pins - if both are 400MHz derived, this could be reasonably valid ? )
So it may be possible to use either a data stream, or a timed-widh, to control CSn, and have it
keep predictable timing relative to streaming data edges ?
100MHz may be possible ?
Given the lack of FLASH on XMOS, and the huge and growing presence of Quad SPI memory, it is surprising that XMOS have still not provided a proven/optimised Quad SPI library ?
More and more Microcontroller vendors are delivering QuadSPI support in hardware.