Review of the XDK SRAM and possibilities

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lilltroll
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Joined: Fri Dec 11, 2009 3:53 am
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Review of the XDK SRAM and possibilities

Post by lilltroll »

So, now I'm up to playing with the SRAM on the XDK, and the XMOS SRAM module v 1.1

I rewrote the program a little to measure the actual transfer rate.
(I'm using a BUFFER_SIZE of 240 in the test, just took it since that is one column on the LCD)

This is the outcome if the SRAM server and the SRAM read write function are located on the same core
writing to SRAM in byte mode...
total time to write 29623us:Eq to 17698kB/s
reading back from SRAM in byte mode to validate it...
total time to write 29607us:Eq to 17708kB/s
test PASS
writing to SRAM in word mode...
total time to write 14945us:Eq to 35081kB/s
reading back from SRAM in word mode to validate it...
total time to write 12855us:Eq to 40784kB/s
test PASS
writing to SRAM in single word...
total time to write 50462us:Eq to 10389kB/s
reading back from SRAM in single word to validate it...
total time to write 47677us:Eq to 10996kB/s
test PASS


If I move the SRAM read write function to an other core the performace looks like this
test iteration 0
writing to SRAM in byte mode...
total time to write 29825us:Eq to 17578kB/s
reading back from SRAM in byte mode to validate it...
total time to write 29793us:Eq to 17597kB/s
test PASS
writing to SRAM in word mode...
total time to write 14997us:Eq to 34959kB/s
reading back from SRAM in word mode to validate it...
total time to write 14661us:Eq to 35760kB/s
test PASS
writing to SRAM in single word...
total time to write 61931us:Eq to 8465kB/s
reading back from SRAM in single word to validate it...
total time to write 56688us:Eq to 9248kB/s
test PASS


I do not know which SRAM chip that is fitted on the XDK but a comment in the code suggests it's a "12ns chip"

A look at a piece of code looks like this:

Code: Select all

p_sram_ctl <: SRAM_CTL_PORT_RD;
   // read with address.
   p_sram_addr <: Adrs;
   sync(p_sram_addr);
   // increment address for next time.
   Adrs += 1;
   p_sram_data :> Temp;
   p_sram_data :> >> Data;   // Read first Byte
   // read with address.
You write the Read/Write port, you write the Adress, but then it seems to be some dead-time used for updating the adress-pointer and also

p_sram_data :> Temp;

Before the actual readout of the SRAM

p_sram_data :> >> Data;

If it's a 12 ns SRAM, why fit the line p_sram_data :> Temp; since several 10ns instructions has passed anyway after the p_sram_addr <: Adrs; line


Probably not the most confused programmer anymore on the XCORE forum.
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larry
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Joined: Fri Mar 12, 2010 6:03 pm

Post by larry »

lilltroll wrote:I do not know which SRAM chip that is fitted on the XDK but a comment in the code suggests it's a "12ns chip"
Hi lilltroll

It's a Samsung K6X4008T1F. This information will go in a hardware manual which we haven't released for the XDK kit yet, but are planning on doing

Datasheet: http://www.datasheetcatalog.org/datashe ... 557_DS.pdf

Of course the comment in the code is wrong. 12ns would be highly unusual for an SRAM like this.
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lilltroll
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Joined: Fri Dec 11, 2009 3:53 am
Location: Sweden, Eskilstuna

Post by lilltroll »

larry wrote:
lilltroll wrote:I do not know which SRAM chip that is fitted on the XDK but a comment in the code suggests it's a "12ns chip"
Hi lilltroll

It's a Samsung K6X4008T1F. This information will go in a hardware manual which we haven't released for the XDK kit yet, but are planning on doing

Datasheet: http://www.datasheetcatalog.org/datashe ... 557_DS.pdf

Of course the comment in the code is wrong. 12ns would be highly unusual for an SRAM like this.
Something I do not understand here. I thought 10 ns has become more common than 12 ns nowadays.
Running at 100 MHz, I was wondering why using 12ns instead of 10 ns - that was the beginning

Farnell sees to have the same amount of different 10 ns SRAM as 55 ns, and it's not a large percentage difference on the price !?
I'm I missing something like waitstate or ?
Here is a not extremely expensive 10 ns 512x8 ASYNC SRAM as an example
http://www.farnell.com/datasheets/86258.pdf
Probably not the most confused programmer anymore on the XCORE forum.
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