Clocked input timing question

[kster59]

XMOS has implemented SPI mode 3 but I need mode 0.
typedef struct spi_master_interface {
clock blk1;
clock blk2;
out buffered port:8 mosi;
out buffered port:8 sclk;
in buffered port:8 miso;
} spi_master_interface;

I made the following modifications to init:
void spi_init(spi_master_interface &i, int spi_clock_div)
{
// configure ports and clock blocks
configure_clock_rate(i.blk1, 100, spi_clock_div);
configure_out_port(i.sclk, i.blk1, 0);
configure_clock_src(i.blk2, i.sclk);
configure_out_port(i.mosi, i.blk2, 0);
configure_in_port(i.miso, i.blk2);
clearbuf(i.mosi);
clearbuf(i.sclk);
start_clock(i.blk1);
start_clock(i.blk2);

// i.sclk <: 0xFF; //mode 3, mode 0, clk = 0
}

In the output and SPI input commands, I am a bit confused about the order of operations.

Writing seems to be ok.

Consider:
i.mosi <: x;
i.sclk <: 0x55;
i.sclk <: 0x55;

I assume bit 0 of X written first then bit 1 is clocked out on the next falling edge

The goal is read on first clock edge

Consider:
i.miso :> x; // samples on rising edge of sclk
i.sclk <: 0x55;
i.sclk <: 0x55;

Is this legal in that line 1 will not pause and line 2 will execute or will it stall on line 1 and never execute line 2?

If I do:
i.sclk <: 0x55;
i.sclk <: 0x55;
i.miso :> x;

then I'm pretty sure it will miss the first clock of sclk.

Is my only option then:
i.sclk <: 0xAA; //0 first then 1
i.sclk <: 0xAA;
sync(sclk);
i.miso :> x;
partout(i.sclk,1,0); //write last bit of clk to reset to 0

This seems less than ideal because it will be much slower due to the last bit write. Any other options?

[matrix]

Hi,

If you need SPI Mode 0, you could check out my topic.

I think I got it right on the last sample code.

However, I could not verify it with a physical slave device, I am
a bit under time pressure with other projects.

Matrix

[matrix]

Performance could be an issue, since a port configuration
is done on every transfer, according to MSB state of
data. I can imagine there is more efficient way of implementation.