Clock generation question

Technical questions regarding the XTC tools and programming with XMOS.
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Lele
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Joined: Mon Oct 31, 2011 4:08 pm
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Clock generation question

Post by Lele »

I was trying to generate four 100MHz clock ( 5ns low 5ns high ) with 1/4 period shift (2,5ns) each other at four different 1 bit out ports.
I succeed (at least on simulator) with following code but I had to set ReferenceFrequency="200Mhz" in the .xn file.
Is my code legal/correct?

Code: Select all

#include <platform.h>

out port ClkPort[] = { XS1_PORT_1I, XS1_PORT_1J, XS1_PORT_1K, XS1_PORT_1L };
clock Clk = XS1_CLKBLK_1;

int main(void)
{
  timer tmr;
  unsigned t;

  configure_clock_rate(Clk, 100, 1);
  for(t=0; t < 4; t++)
  {
    configure_port_clock_output(ClkPort[t], Clk);
    set_pad_delay(ClkPort[t], t);
  }
  start_clock(Clk);

  tmr :> t; /* for debug, just to stop simulation after a while */
  t += 1000;
  tmr when timerafter(t) :> void;
  return 0;
}
Could be done without ReferenceFrequency="200Mhz"?
Tried to set Clk = XS1_CLKBLK_REF; but had "invalid resource used" by compiler althought I saw XS1_CLKBLK_REF used in some examples?
Is set_pad_delay usage correct or it should be used only to delay inputs?

Sorry for my many questions but I'am newbie to xmos processor.


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Ross
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Joined: Thu Dec 10, 2009 9:20 pm
Location: Bristol, UK

Post by Ross »

Lele wrote: Is set_pad_delay usage correct or it should be used only to delay inputs?
Yes, just for input (see xs1.h)

Code: Select all

/** Sets the delay on the pins connected to the port. The input signals sampled on the
 *  port's pins are delayed by this number of processor-clock cycles before they
 *  they are seen on the port. The default delay on the pins is 0.
 *  The delay must be set to values in the range 0 to 5 inclusive.
 *  If there are multiple enabled ports connected to the same pin then the delay
 *  on that pin is set by the highest priority port.
 *  \param p The port to configure.
 *  \param n The number of processor-clock cycles by which to delay the input
 *           signal.
 */
Maybe take a look at delaying clockblock ticks using set_clock_fall_delay()

R
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Lele
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Joined: Mon Oct 31, 2011 4:08 pm
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Post by Lele »

Tanks Ross,

I had the suspect that set_pad_delay works only for input, but surprisingly in simulation it worked for output too, may be hw is capable to do it too. Could not verify on real board because I don't have an oscilloscope.
Using set_clock_rise/fall_delay would would act at clock source so I "waste" 4 clock blocks.

Lele
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