Error XN11049 with more than 2 L2's

Technical questions regarding the XTC tools and programming with XMOS.
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Paolomio
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Joined: Tue Oct 05, 2010 7:33 pm

Error XN11049 with more than 2 L2's

Post by Paolomio »

I have a system in development that will have a total of 16 L2's. In trying to create the XN file for this beast I find that the compiler throws the dreaded XN11049 error when I try to connect a 3rd L2. My XN file looks like:

Code: Select all

<?xml version="1.0" encoding="UTF-8"?>
<Network xmlns="http://www.xmos.com"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.xmos.com http://www.xmos.com">

  <Declarations>
    <Declaration>core stdcore[6]</Declaration>
  </Declarations>

  <Packages>
    <Package ID="0" Type="XS1-L2A-QF124">
	  <Nodes>
	    <Node Id="0" Type="XS1-L1A" InPackageId="0" Oscillator="20MHz" SystemFrequency="500MHz" ReferenceFrequency="100MHz">
	      <Core Number="0" Reference="stdcore[0]">
	        <Port Location="XS1_PORT_1A" Name="PORT_SPI_MISO0"/>
	        <Port Location="XS1_PORT_1B" Name="PORT_SPI_SS0"/>
	        <Port Location="XS1_PORT_1C" Name="PORT_SPI_CLK0"/>
	        <Port Location="XS1_PORT_1D" Name="PORT_SPI_MOSI0"/>
	      </Core>
	      <Boot>
	      	<Source Location="SPI:bootFlash0"></Source>
	      	<Bootee NodeID="1"></Bootee>
	      </Boot>
	    </Node>
	    <Node Id="1" Type="XS1-L1A" InPackageId="1" Oscillator="20MHz" SystemFrequency="500MHz" ReferenceFrequency="100MHz">
	      <Core Number="0" Reference="stdcore[1]">
	      </Core>
	      <Boot>
	    	  <Source Location="XMOSLINK"></Source>
	      </Boot>
	    </Node>
	  </Nodes>
    </Package>
    
    <Package ID="0" Type="XS1-L2A-QF124">
	  <Nodes>
	    <Node Id="2" Type="XS1-L1A" InPackageId="0" Oscillator="20MHz" SystemFrequency="500MHz" ReferenceFrequency="100MHz">
	      <Core Number="0" Reference="stdcore[2]">
	        <Port Location="XS1_PORT_1A" Name="PORT_SPI_MISO2"/>
	        <Port Location="XS1_PORT_1B" Name="PORT_SPI_SS2"/>
	        <Port Location="XS1_PORT_1C" Name="PORT_SPI_CLK2"/>
	        <Port Location="XS1_PORT_1D" Name="PORT_SPI_MOSI2"/>
	      </Core>
	      <Boot>
	      	<Source Location="SPI:bootFlash2"></Source>
	      	<Bootee NodeID="3"></Bootee>
	      </Boot>
	    </Node>
	    <Node Id="3" Type="XS1-L1A" InPackageId="1" Oscillator="20MHz" SystemFrequency="500MHz" ReferenceFrequency="100MHz">
	    	<Core Number="0" Reference="stdcore[3]">
	    	</Core>
	    	<Boot>
	    		<Source Location="XMOSLINK"></Source>
	    	</Boot>
	    </Node>
	  </Nodes>
    </Package>
  
    <Package ID="0" Type="XS1-L2A-QF124">
	  <Nodes>
	    <Node Id="4" Type="XS1-L1A" InPackageId="0" Oscillator="20MHz" SystemFrequency="500MHz" ReferenceFrequency="100MHz">
	      <Core Number="0" Reference="stdcore[4]">
	        <Port Location="XS1_PORT_1A" Name="PORT_SPI_MISO4"/>
	        <Port Location="XS1_PORT_1B" Name="PORT_SPI_SS4"/>
	        <Port Location="XS1_PORT_1C" Name="PORT_SPI_CLK4"/>
	        <Port Location="XS1_PORT_1D" Name="PORT_SPI_MOSI4"/>
	      </Core>
	      <Boot>
	      	<Source Location="SPI:bootFlash4"></Source>
	      	<Bootee NodeID="5"></Bootee>
	      </Boot>
	    </Node>
	    <Node Id="5" Type="XS1-L1A" InPackageId="1" Oscillator="20MHz" SystemFrequency="500MHz" ReferenceFrequency="100MHz">
	    	<Core Number="0" Reference="stdcore[5]">
	    	</Core>
	    	<Boot>
	    		<Source Location="XMOSLINK"></Source>
	    	</Boot>
	    </Node>
	  </Nodes>
    </Package>
  </Packages>

  <Links>
	<Link Encoding="5wire" Delays="0,1">
      <LinkEndpoint NodeId="0" Link="X1LC"/>
      <LinkEndpoint NodeId="1" Link="X1LB"/>
    </Link>
    <Link Encoding="5wire" Delays="0,1">
      <LinkEndpoint NodeId="0" Link="X1LD"/>
      <LinkEndpoint NodeId="1" Link="X1LA"/>
    </Link>
    <Link Encoding="5wire" Delays="0,1">
      <LinkEndpoint NodeId="0" Link="X1LA"/>
      <LinkEndpoint NodeId="1" Link="X1LD"/>
    </Link>
    <Link Encoding="5wire" Delays="0,1">
      <LinkEndpoint NodeId="0" Link="X1LB"/>
      <LinkEndpoint NodeId="1" Link="X1LC"/>
    </Link>
    
    <Link Encoding="2wire" Delays="0,1">
      <LinkEndpoint NodeId="0" Link="X0LB"/>
      <LinkEndpoint NodeId="2" Link="X0LA"/>
    </Link>
    
    <Link Encoding="5wire" Delays="0,1">
      <LinkEndpoint NodeId="2" Link="X1LC"/>
      <LinkEndpoint NodeId="3" Link="X1LB"/>
    </Link>
    <Link Encoding="5wire" Delays="0,1">
      <LinkEndpoint NodeId="2" Link="X1LD"/>
      <LinkEndpoint NodeId="3" Link="X1LA"/>
    </Link>
    <Link Encoding="5wire" Delays="0,1">
      <LinkEndpoint NodeId="2" Link="X1LA"/>
      <LinkEndpoint NodeId="3" Link="X1LD"/>
    </Link>
    <Link Encoding="5wire" Delays="0,1">
      <LinkEndpoint NodeId="2" Link="X1LB"/>
      <LinkEndpoint NodeId="3" Link="X1LC"/>
    </Link>
    
    <Link Encoding="2wire" Delays="0,1">
      <LinkEndpoint NodeId="2" Link="X0LB"/>
      <LinkEndpoint NodeId="4" Link="X0LA"/>
    </Link>
    
    <Link Encoding="5wire" Delays="0,1">
      <LinkEndpoint NodeId="4" Link="X1LC"/>
      <LinkEndpoint NodeId="5" Link="X1LB"/>
    </Link>
    <Link Encoding="5wire" Delays="0,1">
      <LinkEndpoint NodeId="4" Link="X1LD"/>
      <LinkEndpoint NodeId="5" Link="X1LA"/>
    </Link>
    <Link Encoding="5wire" Delays="0,1">
      <LinkEndpoint NodeId="4" Link="X1LA"/>
      <LinkEndpoint NodeId="5" Link="X1LD"/>
    </Link>
    <Link Encoding="5wire" Delays="0,1">
      <LinkEndpoint NodeId="4" Link="X1LB"/>
      <LinkEndpoint NodeId="5" Link="X1LC"/>
    </Link>
  </Links>

<ExternalDevices>
    <Device NodeId="0" Core="0" Class="SPIFlash" Name="bootFlash0" Type="34">
      <Attribute Name="PORT_SPI_MISO" Value="PORT_SPI_MISO0" />
      <Attribute Name="PORT_SPI_SS" Value="PORT_SPI_SS0" />
      <Attribute Name="PORT_SPI_CLK" Value="PORT_SPI_CLK0" />
      <Attribute Name="PORT_SPI_MOSI" Value="PORT_SPI_MOSI0" />
    </Device>
    
    <Device NodeId="2" Core="0" Class="SPIFlash" Name="bootFlash2" Type="34">
      <Attribute Name="PORT_SPI_MISO" Value="PORT_SPI_MISO2" />
      <Attribute Name="PORT_SPI_SS" Value="PORT_SPI_SS2" />
      <Attribute Name="PORT_SPI_CLK" Value="PORT_SPI_CLK2" />
      <Attribute Name="PORT_SPI_MOSI" Value="PORT_SPI_MOSI2" />
    </Device>
    
    <Device NodeId="4" Core="0" Class="SPIFlash" Name="bootFlash4" Type="34">
      <Attribute Name="PORT_SPI_MISO" Value="PORT_SPI_MISO4" />
      <Attribute Name="PORT_SPI_SS" Value="PORT_SPI_SS4" />
      <Attribute Name="PORT_SPI_CLK" Value="PORT_SPI_CLK4" />
      <Attribute Name="PORT_SPI_MOSI" Value="PORT_SPI_MOSI4" />
    </Device>
</ExternalDevices>
  
  <JTAGChain>
     <JTAGDevice NodeId="0"/>
     <JTAGDevice NodeId="1"/>
     <JTAGDevice NodeId="2"/>
     <JTAGDevice NodeId="3"/>
     <JTAGDevice NodeId="4"/>
     <JTAGDevice NodeId="5"/>
  </JTAGChain>
 
</Network>
I am using version 11.11.1 of the tools. This is because we have 100K+ lines of legacy code, including the original Ethernet stack. We cannot switch to a newer compiler because the XMOS-supplied Ethernet stack will not build on later tools, and the newer Ethernet stack lacks features we require and is very different in API to the older one.

So I need to find a way to have more than 2 L2s in an XN file using 11.11.1. Anyone done this before? Or is this another thing that the tools do not handle properly?

Thanks,

Paul


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johned
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Post by johned »

Hi,
This shouldn't be a problem, at all.
Have you had a look at this project that networks 4 devices (the old G4s) :
https://github.com/tomcarter259/Quad-XC-1A

Best regards,
John
Redeye
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Posts: 131
Joined: Wed Aug 03, 2011 9:13 am

Post by Redeye »

Due to a similar situation I'm stuck on v13.2 tools. I have got a 3xL2 + 1xL1 board which compiles/runs fine on 13.2.

It's a while ago that I created the XN file - I seem to remember a bit of trial and error to get it right. I think what I did was create a very basic shell application which ran an endless loop on each core, then by trial and error got the XN file working before I started worrying about real code.

Just had a quick look through your XN file - it looks like you've got all the packages with an ID of 0. I think you probably need package ID's of 1 and 2 for the second and third processors? Not sure if that's the problem, but I appreciate that the compiler errors aren't particularly helpful to diagnose it.
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Paolomio
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Joined: Tue Oct 05, 2010 7:33 pm

Post by Paolomio »

Redeye wrote:It's a while ago that I created the XN file - I seem to remember a bit of trial and error to get it right. I think what I did was create a very basic shell application which ran an endless loop on each core, then by trial and error got the XN file working before I started worrying about real code.

Just had a quick look through your XN file - it looks like you've got all the packages with an ID of 0. I think you probably need package ID's of 1 and 2 for the second and third processors? Not sure if that's the problem, but I appreciate that the compiler errors aren't particularly helpful to diagnose it.
Hi Redeye,

I've been doing something similar, trying to get this to compile. I don't know if the package ID's need to be different--I tried that and it made no difference to this issue.

Can you share your XN file? I have a sinking feeling that this doesn't work properly with 11.11.1, but if you have an XN file that does work with your tools I can try it and see if that's the problem.

Thanks!

Paul
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Paolomio
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Posts: 64
Joined: Tue Oct 05, 2010 7:33 pm

Post by Paolomio »

Hi John,

Thanks for the tip. However, I am using L2's, not G4's, and so the topology is different. I assume the compiler handles L2's and G4's differently, since their switches are so different.

Can you please (a) take a look at the XN file that I posted to see what I might be doing wrong, (b) confirm that someone has actually connected more than 2 L2's in series, and (c) if that's been done, provide an example XN file that does that?

Thanks!

Paul
Redeye
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Posts: 131
Joined: Wed Aug 03, 2011 9:13 am

Post by Redeye »

Paul,

I've got a horrible feeling you're right about 11.11.1 not supporting this properly.

I've put my 7 core XN file below. You'll probably need to change a couple of things ("tile" to "stdcore" and the packages/nodes had different codes in v11 I think), but otherwise I think the syntax has stayed pretty constant.

Code: Select all

<?xml version="1.0" encoding="UTF-8"?>
<Network xmlns="http://www.xmos.com"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.xmos.com http://www.xmos.com">
  <Type>Board</Type>
  <Name>X</Name>
  <!-- Board Version 1V0 -->
  <!-- File Version 1V0 -->

  <Declarations>
    <Declaration>tileref tile[7]</Declaration>
  </Declarations>

  <Packages>
    <Package ID="0" Type="XS1-LnA-64-LQ64">
      <Nodes>
       <Node Id="0" Type="XS1-L8A-64" InPackageId="0" Oscillator="25MHz" SystemFrequency="400MHz">
          <Core Number="0" Reference="tile[0]">	 		
          </Core>
          <Boot>
             <Source Location="XMOSLINK"></Source>
          </Boot>
       </Node>
     </Nodes>
    </Package>
    <Package ID="1" Type="XS1-L2A-QF124">
	  <Nodes>
        <Node Id="1" Type="XS1-L8A-64" InPackageId="0" Oscillator="25MHz" SystemFrequency="500MHz">
		  <Boot>
			<Source Location="SPI:bootFlash"/>
			<Bootee NodeId="0"/>
			<Bootee NodeId="2"/>
			<Bootee NodeId="3"/>
			<Bootee NodeId="4"/>
			<Bootee NodeId="5"/>
			<Bootee NodeId="6"/>
		  </Boot>
		  <Core Number="0" Reference="tile[1]">
			<!-- SPI FLASH -->
			<Port Location="XS1_PORT_1A" Name="PORT_SPI_FLASH_MISO"/>
			<Port Location="XS1_PORT_1B" Name="PORT_SPI_FLASH_SS"/>
			<Port Location="XS1_PORT_1C" Name="PORT_SPI_FLASH_CLK"/>
			<Port Location="XS1_PORT_1D" Name="PORT_SPI_FLASH_MOSI"/>			
		  </Core>
		</Node>
        <Node Id="2" Type="XS1-L8A-64" InPackageId="1" Oscillator="25MHz" SystemFrequency="500MHz">
		  <Boot>
			<Source Location="XMOSLINK"/>
		  </Boot>
		  <Core Number="0" Reference="tile[2]">
			
		  </Core>
		</Node>
	  </Nodes>
    </Package>
    <Package ID="2" Type="XS1-L2A-QF124">
      <Nodes>
       <Node Id="3" Type="XS1-L8A-64" InPackageId="0" Oscillator="25MHz" SystemFrequency="500MHz">
          <Core Number="0" Reference="tile[3]">	
          </Core>
          <Boot>
             <Source Location="XMOSLINK"></Source>
          </Boot>
       </Node>
       <Node Id="4" Type="XS1-L8A-64" InPackageId="1" Oscillator="25MHz" SystemFrequency="500MHz">
          <Core Number="0" Reference="tile[4]">
          </Core>
          <Boot>
             <Source Location="XMOSLINK"></Source>
          </Boot>
        </Node>
     </Nodes>
    </Package>
    <Package ID="4" Type="XS1-L2A-QF124">
      <Nodes>
       <Node Id="5" Type="XS1-L8A-64" InPackageId="0" Oscillator="25MHz" SystemFrequency="500MHz">
          <Core Number="0" Reference="tile[5]">	
          </Core>
          <Boot>
             <Source Location="XMOSLINK"></Source>
          </Boot>
       </Node>
       <Node Id="6" Type="XS1-L8A-64" InPackageId="1" Oscillator="25MHz" SystemFrequency="500MHz">
          <Core Number="0" Reference="tile[6]">
          </Core>
          <Boot>
             <Source Location="XMOSLINK"></Source>
          </Boot>
        </Node>
     </Nodes>
    </Package>
  </Packages>

  <Links>
    <!-- XScope -->
    <Link Encoding="2wire" Delays="4,4" Flags="XSCOPE">
      <LinkEndpoint NodeId="6" Link="X0LB"/>
      <LinkEndpoint RoutingId="0x8000" Chanend="1"/>
    </Link>
    <!-- L2 Internal L2-0 -->
    <Link Encoding="5wire" Delays="0,1">
      <LinkEndpoint NodeId="1" Link="4"/>
      <LinkEndpoint NodeId="2" Link="7"/>
    </Link>
    <Link Encoding="5wire" Delays="0,1">
      <LinkEndpoint NodeId="1" Link="5"/>
      <LinkEndpoint NodeId="2" Link="6"/>
    </Link>
    <Link Encoding="5wire" Delays="0,1">
      <LinkEndpoint NodeId="1" Link="6"/>
      <LinkEndpoint NodeId="2" Link="5"/>
    </Link>
    <Link Encoding="5wire" Delays="0,1">
      <LinkEndpoint NodeId="1" Link="7"/>
      <LinkEndpoint NodeId="2" Link="4"/>
    </Link>
    <!-- L2 Internal L2-1 -->
    <Link Encoding="5wire" Delays="0,1">
      <LinkEndpoint NodeId="3" Link="4"/>
      <LinkEndpoint NodeId="4" Link="7"/>
    </Link>
    <Link Encoding="5wire" Delays="0,1">
      <LinkEndpoint NodeId="3" Link="5"/>
      <LinkEndpoint NodeId="4" Link="6"/>
    </Link>
    <Link Encoding="5wire" Delays="0,1">
      <LinkEndpoint NodeId="3" Link="6"/>
      <LinkEndpoint NodeId="4" Link="5"/>
    </Link>
    <Link Encoding="5wire" Delays="0,1">
      <LinkEndpoint NodeId="3" Link="7"/>
      <LinkEndpoint NodeId="4" Link="4"/>
    </Link>
    <!-- L2 Internal L2-2 -->
    <Link Encoding="5wire" Delays="0,1">
      <LinkEndpoint NodeId="5" Link="4"/>
      <LinkEndpoint NodeId="6" Link="7"/>
    </Link>
    <Link Encoding="5wire" Delays="0,1">
      <LinkEndpoint NodeId="5" Link="5"/>
      <LinkEndpoint NodeId="6" Link="6"/>
    </Link>
    <Link Encoding="5wire" Delays="0,1">
      <LinkEndpoint NodeId="5" Link="6"/>
      <LinkEndpoint NodeId="6" Link="5"/>
    </Link>
    <Link Encoding="5wire" Delays="0,1">
      <LinkEndpoint NodeId="5" Link="7"/>
      <LinkEndpoint NodeId="6" Link="4"/>
    </Link>
    <!-- L2 External L1 to L2-0 -->
    <Link Encoding="2wire" Delays="8,8">
      <LinkEndpoint NodeId="0" Link="X0LB"/>
      <LinkEndpoint NodeId="1" Link="X0LB"/>
    </Link>
    <!-- L2 External L2-0 to L2-1 -->
    <Link Encoding="5wire" Delays="4,4">
      <LinkEndpoint NodeId="2" Link="X0LA"/>
      <LinkEndpoint NodeId="3" Link="X0LA"/>
    </Link>
    <Link Encoding="5wire" Delays="4,4">
      <LinkEndpoint NodeId="2" Link="X0LB"/>
      <LinkEndpoint NodeId="3" Link="X0LB"/>
    </Link>
    <!-- L2 External L2-1 to L2-2 -->
    <Link Encoding="5wire" Delays="4,4">
      <LinkEndpoint NodeId="4" Link="X0LA"/>
      <LinkEndpoint NodeId="5" Link="X0LA"/>
    </Link>
    <Link Encoding="5wire" Delays="4,4">
      <LinkEndpoint NodeId="4" Link="X0LB"/>
      <LinkEndpoint NodeId="5" Link="X0LB"/>
    </Link>
  </Links>

  <ExternalDevices>
    <Device NodeId="1" Core="0" Class="SPIFlash" Name="bootFlash" Type="Atmel_AT25DF321A">
      <Attribute Name="PORT_SPI_MISO" Value="PORT_SPI_FLASH_MISO"/>
      <Attribute Name="PORT_SPI_SS"   Value="PORT_SPI_FLASH_SS"/>
      <Attribute Name="PORT_SPI_CLK"  Value="PORT_SPI_FLASH_CLK"/>
      <Attribute Name="PORT_SPI_MOSI" Value="PORT_SPI_FLASH_MOSI"/>
    </Device>
  </ExternalDevices>

  <JTAGChain>
     <JTAGDevice NodeId="1"/>
     <JTAGDevice NodeId="2"/>
     <JTAGDevice NodeId="3"/>
     <JTAGDevice NodeId="4"/>
     <JTAGDevice NodeId="5"/>
     <JTAGDevice NodeId="6"/>
     <JTAGDevice NodeId="0"/>
  </JTAGChain>
 
</Network>
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Paolomio
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Post by Paolomio »

Hi Redeye,

This looks like its on the right track! I had to change some of the package types to match what is available on 11.11.1, and remove the xscope reference, but I'm able to build it.

I suspect the difference is that my old file uses symbolic names for the links, and yours uses numerical names. It would be great to understand what these really mean (the sum total of documentation on this that I have found says something like "there are links labeled A, B, C, D...").

But this gives me something to scratch around with. Thanks!

Paul
Redeye
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Posts: 131
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Post by Redeye »

Great, glad it helped. I can't profess to be an expert on it - there was a lot of trial and error and persistence involved in getting it to work because there aren't actually any example XN files for multiple processor system, which seems a bit strange to me seeing as linking multiple processors is supposed to be one of the headline features of XMOS processors.
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Paolomio
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Post by Paolomio »

"You very well might say that, but I couldn't possibly comment."
-- Francis Urquhart
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Paolomio
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Post by Paolomio »

It looks like the problem is connecting XL0A on a tile to XL0B on another while also connecting XL0A on that 2nd tile to XL0B on a third one. In other words, daisy-chaining three L2 tiles A to B, A to B. Like this:

Code: Select all

     O         O         O
     |         |         |
    OA ------ BOA ----- BO
This shows 3 L2's linked via A<->B in series.

This will not build, but I don't see any reason why not.

If I change it so that XL0A on the 1st one goes to XL0B on the 2nd tile of the 2nd L2 (or any other topology than the one I need) it will compile. However, that is not the topology I need to use.

Is there any way to get this to build?

Paul
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