Schematic of L1 64pin general board something like Xk-1A

Technical questions regarding the XTC tools and programming with XMOS.
jagspaul
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Schematic of L1 64pin general board something like Xk-1A

Post by jagspaul »

I have design it for my L1 based RGB LED tile.
Please go through the schematic and let me know if there any thing wrong? Also put your suggestion. Actually I would like to make a review on this schematic before processing. If you have any queries please feel free to ask me.

Thanks
jags
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Bianco
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Post by Bianco »

You don't have a sequenced power supply, and you are on the edge of what the NCP4588 can dissipate when the XCORE is under heavy load

I'd add a pull-up resistor on the SPI Flash SS line.

Maybe add a real Power-On-Reset Controller?
jagspaul
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Post by jagspaul »

Thanks Bianco for your attention.
Could you please tell me in details about sequenced power supply.

NCP4588 can handle 200ma. Could you tell me what is the maximum requirement of core when XCORE under heavy load?

thanks
jags
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Bianco
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Post by Bianco »

I have never done tests myself but according to the datasheet, you can expect a current draw of 200-225 mA under typical high load and perhaps quite some more in theoretical cases.

Your 200mA LDO will be on the edge of what it can deliver in that case.
Also you can expect that when the LDO delivers 200mA with an input voltage of 3.3V and an output voltage of 1.0V it will have to dissipate at least (3.3-1.0) * 0.2 W or 0.46W. According to the datasheet the SOT23 package can dissipate around 0.42W.

So there is a good chance that when the XCORE is under load your LDO can both not deliver the amount or required current and can not dissipate the heat. You need to design electronics with a certain margin. If you expect a current draw of 200mA, use at least a regulator that can deliver 300mA.

About the sequenced power supplies:

This line in the datasheet is very important:
The VDDIO supply must ramp to its final value before VDD reaches 0.4 V.

It means that the 3.3V supply must start first and after the 3.3V supply is stable the 1.0V supply can be enabled (it should be disabled before that). Best case you use a 3.3V regulator with POWER GOOD output and a 1.0V regulator with ENABLE input and with the POWER GOOD output of the 3.3V regulator tied to the ENABLE input of the 1.0V regulator
jagspaul
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Post by jagspaul »

Thanks Bianco.
Actually I followed the XK-1A schematic and I could not find this power sequence there? How with out power sequence XK-1A is running? Is is not mandatory for L1 128 pin chip?

However I understand NCP4588 is running on edge. But I dont want to use any switching regulator. I like LDO. So could you suggest some LDO suitable for L1 64 pin chip.

thanks & regards
jags
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Bianco
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Post by Bianco »

I want to point you to the L1 Hardware Design Checklist

The XK-1 and XK-1A boards do not follow the recommendations regarding power supply sequencing (and also lacking a real POR). Initially because the XK-1 was released before the issue with power supply sequencing was discovered. It will work on the XK-1 / XK-1A because there is a large chance that the 3V3 regulator ramps up faster than the 1V0 regulator. I think the linear regulator needs less time to start up, and besides that the 1V0 has larger capacitors on the line. I think that when you connect a large capacitor on the expansion port between 3V3 and GND that the XK-1/A will not boot anymore.

For a proper example of an XK-1 system download this zip file http://www.xmos.com/published/xk-1-sche ... ion=latest and see the "new design" PDF. Don't use the XK-1 schematics for the XTAG XMOS Link configuration as it contains a bug (hence the XK-1A saw life)

Any LDO that can supply 300mA or more and has a small heatsink will do a much better job than the LDO in the SOT-23 package. Preferably one with an ENABLE input :)
jagspaul
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Post by jagspaul »

Hi Bianco

What about AP7331. Can you give me some part number of 1.0v LDO?
Please give some idea, how to make power sequence.

jags
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jagspaul
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Post by jagspaul »

AP7331.JPG
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AP7331.JPG
AP7331.JPG (13.11 KiB) Viewed 4882 times
Hi Bianco

My target is to make design cost as low as possible.
Please go through the attach diagram and let me know how is this power sequencer. The 3.3 V LDO get stable first and that time RC network keep EN pin of 1.0 V LDO low. After a delay it will make EN high and 1.0 V LDO start.
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Bianco
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Post by Bianco »

That will work if cost is an issue
jagspaul
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Post by jagspaul »

Hi bianco,
Please tell me about reset sequence.
When reset should be released? After stable of 3.3V or 1.0v?

After release of reset what should be the reset pin voltage 1.0V or 3.3V ?

jags
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