Simulating an external clock in XS1-L1 USB Audio Ref. Design

[xcoreuser]

Hello,

I'm trying to simulate the USB Audio reference design for XS1-L1 in the XDE simulator (app_usb_aud_l1 application and related modules). Apparently, the simulation starts, but the device ports in the waveform seem to be stuck at zero after going in use, particularly those connected to the audio Codec (CODEC is configured as slave). I guess this depends on the fact that there is no external master clock on input port 1M. I'm not very familiar with the XDE environment, so the only way I could figure out to simulate an external clock (apart from writing a simulator plug-in) is to output a clock from the XS1 device and loopback it to the 1M input port. I added the following code to the app_usb_aud_l1 application main file (main.xc):

on stdcore[0] : clock myClk = XS1_CLKBLK_1; // midi was disabled, so I used the midi clkblk
...
out port myOutClock = XS1_PORT_1G ;
...
int main(){
...
configure_clock_rate (myClk , 100 , 4) ;
configure_port_clock_output ( myOutClock , myClk );
start_clock ( myClk );

However, although it goes in use, the output port (here 1G) sticks at zero. This also happens when I try to generate manually some output sequences from an additional thread that sets some unused port. It seems that something prevents the XS1-L1 ports from being affected by the XC code. By the way, I managed to generate some sequences on output ports from my thread, but only on those ports that are not available in the simulated package (e.g. port 16D).

Do you have any clue on why ports are not affected by assignments in the USB audio XS1-L1 reference design and/or on how to simulate an external clock signal to drive the design?
Thanks a lot!

[Ross]

Is there something in particular you were looking to simulate? Simulating the whole USB Audio reference design would be a very large task. For example, what will model the USB phy?

[xcoreuser]

Hi Ross,
thank you for your reply. In fact, I'm just interested in testing the behaviour of the I2S interface with the Codec, both in codec-slave and codec-master mode. I expected the 'p_lrclk' and 'p_bclk' clocks going from the XS1 device to the codec in codec-slave mode to be driven even if there is nothing connected to the USB part of the design, but I'm realizing this may not be necessarly the case... Was I wrong?

Anyway, in the "audioports.xc" file of the "module_usb_aud_shared" module, I replaced the following line:

configure_clock_src(clk_audio_mclk, p_mclk);

with this line:

configure_clock_rate(clk_audio_mclk , 100 , 4) ; // don't mind the clock frequency for now

just to emulate the external clock which is supposed to be input from the outside through the 'p_mclk' port, i.e. port 1M. The clock block 'clk_audio_mclk' (connected to the the clock block 2) is correctly set and its rising/falling edges are displayed in the waveform at the expected frequency. However, any other ports that should depend on this clock do not seem to be influenced.
For example, in the same file, right after the above call, you can find this piece of code:

if (divide == 1) {
configure_port_clock_output(p_bclk, clk_audio_mclk);
}
else{
configure_out_port_no_ready(p_bclk, clk_audio_mclk, 0);
}

I even replaced it with this unconditional call:
configure_port_clock_output(p_bclk, clk_audio_mclk);

In neither case the "p_bclk" seems to be be affected by the clock on 'clk_audio_mclk'.

I didn't totally reverse-engineered the code and I see there may be some other part of the design influencing the I2S interface with the Coded, but I still suspect there's some general problem preventing the ports from behaving as espected. I came to this (perhaps wrong) conclusion as I tried to manually control some ports by adding my own code in the same design, so that it shouldn't be influenced by any other piece of code (e.g. a thread started in the main.xc file, attempting to set some unused port, as I explained in my previous post), but even in this case the ports stick at zero. They only change their 'in use' property when expected.

Of course, if I create a new design from scratch, the ports are set as expected. This is really driving me crazy.

Thank you very much for your help!