Hello
i try to understand the MII-part of the module_ethernet implementation.
within the mii_init_full function the used ports and clockblocks are configured to use defined delays.
Even if the delays are defined to be zero i start wondering how it works internally.
at first the RX-Clk input signal is set by using set_pad_delay(). After that, the RX-Clk input port is used as reference for the clk_mii_rx clockblock.
What i assume is:
When the RX-Clk input signal occurs the occurrence of the clk_mii_rx clockblock is delayed by the pad_delay.
At next the clk_mii_rx clockblock is configured to use a rise-delay (set_clock_rise_delay)
My further assumption is:
The rising of the clockblock is delayed in addition to the pad delay (proportional to the RX-Clk input signal).
Am i right so far?
If not, would you please be so kind and correct me?
Greetings Vanilla
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