Ethernet & xSoftip

Post by **Folknology** » Thu Aug 08, 2013 12:31 pm

I would just like to clarify something regarding a project I working on that may require onboard MII Ethernet and its been a while since I looked at the MII side of things with Xmos.

If I run xSoftip and add Layer 2 Ethernet Mac, under resources it claims to require:

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2 logical cores
9.9K
5 x 1bit ports
3 x 4 bit ports
1 x 8 bit port
2 clk blocks
8 chanends
2 Timers

I have also chosen to combine SMI ports on single port and not use reset port.

This seems to use more ports than I was previously accustomed to. So I then looked at the hardware manual for the Ethernet Slice and notice it only uses the following ports:

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/********************************************
* 4 x 1 bit ports RXDV,RXCLK,TXCLK,TXEN
* 2 x 4bit ports for RX0-3 and TX0-3
* 1/2 X 8 bit port for MDIO,MDC,INTN,RXERR 
********************************************/

#if defined(ETHERNET_USE_SQUARE_SLOT)
#define SMI_COMBINE_MDC_MDIO 1
#define SMI_MDC_BIT 0
#define SMI_MDIO_BIT 1
#define ETHERNET_DEFAULT_TILE tile[1]
#define PORT_ETH_RXCLK on tile[1]: XS1_PORT_1B
#define PORT_ETH_RXD on tile[1]: XS1_PORT_4A
#define PORT_ETH_TXD on tile[1]: XS1_PORT_4B
#define PORT_ETH_RXDV on tile[1]: XS1_PORT_1C
#define PORT_ETH_TXEN on tile[1]: XS1_PORT_1F
#define PORT_ETH_TXCLK on tile[1]: XS1_PORT_1G
#define PORT_ETH_MDIOC on tile[1]: XS1_PORT_4C
#define PORT_ETH_MDIOFAKE on tile[1]: XS1_PORT_8A
#define PORT_ETH_ERR on tile[1]: XS1_PORT_4D

*Update here is the Ethernet slicekit board conf the square slot config is closest to my config, although I don't quite get the 'MDIOFake' business

This is significantly less than xSoftip suggests and more what I expected from my pre-xSoftip experiences. It is important in this particular project because I have only a few ports available for the MII Ethernet interfacing, I would like to use the same port sizes as the Ethernet slice except I would like to exchange the half 8bit port for another 4 bit port, is this likely to work ok with the current xCore Github libraries?

I have ports 8A and 8B as well as at least 4 x 1 bit ports available, although I would like to use 4B or 4D for xScope if possible (can be sacrificed to make MII work), something like this perhaps?

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#if defined(ALS_FALLBACK_OPTION)
#define SMI_COMBINE_MDC_MDIO 1
#define SMI_MDC_BIT 0
#define SMI_MDIO_BIT 1
#define ETHERNET_DEFAULT_TILE tile[1]
#define PORT_ETH_RXCLK on tile[1]: XS1_PORT_1A
#define PORT_ETH_RXD on tile[1]: XS1_PORT_4A
#define PORT_ETH_TXD on tile[1]: XS1_PORT_4B
#define PORT_ETH_RXDV on tile[1]: XS1_PORT_1B
#define PORT_ETH_TXEN on tile[1]: XS1_PORT_1C
#define PORT_ETH_TXCLK on tile[1]: XS1_PORT_1D
#define PORT_ETH_MDIOC on tile[1]: XS1_PORT_4C
#define PORT_ETH_MDIOFAKE on tile[1]: XS1_PORT_8A
#define PORT_ETH_ERR on tile[1]: XS1_PORT_4D  // jumpered along with INT to allow xScoping

#else

#if defined(ALS_PREFERRED_OPTION)
#define SMI_COMBINE_MDC_MDIO 1
#define SMI_MDC_BIT 0
#define SMI_MDIO_BIT 1
#define ETHERNET_DEFAULT_TILE tile[1]
#define PORT_ETH_RXCLK on tile[1]: XS1_PORT_1A
#define PORT_ETH_RXD on tile[1]: XS1_PORT_4A
#define PORT_ETH_TXD on tile[1]: XS1_PORT_4D
#define PORT_ETH_RXDV on tile[1]: XS1_PORT_1B
#define PORT_ETH_TXEN on tile[1]: XS1_PORT_1C
#define PORT_ETH_TXCLK on tile[1]: XS1_PORT_1D
#define PORT_ETH_MDIOC on tile[1]: XS1_PORT_4C
#define PORT_ETH_MDIOFAKE on tile[1]: XS1_PORT_8B
#define PORT_ETH_ERR on tile[1]: XS1_PORT_4B // jumpered along with INT to allow xScoping

Will either of these options work, can anyone explain the 'fake' business, can it be any port?

Are their any assumptions about XS1 core clock speed?

regards
Al