Looking at the dissassembly I see:
FillPin <: AllOnes;
becomes;
ldwdp (lru6) r2, dp
out (r2r) res[r2], r11
Is there a way of getting FillPin and ClearPin to be register variables, so that instructions such as "r2, dp" will not be created?. This would considerably speed things up.
Code: Select all
[size=85][color=#0000FF] {
on stdcore [0] : out buffered port:32 ClearPin = PortClearPin ;
on stdcore [0] : out buffered port:32 FillPin = PortFillPin;
<-------snip-------->
register unsigned long NFB,NCB,FillBits,ClearBits1,ClearBits2;
register unsigned long AllOnes,AllZeroes;
<----- snip ------->
FillPin <: AllOnes;
ClearPin <: AllZeroes;
NFB = NFB - 1;
start_clock(clk);
while (NFB != 0)
{
FillPin <: AllOnes;
ClearPin <: AllZeroes;
NFB = NFB - 1;
}
FillPin <: FillBits;
ClearPin <: ClearBits1;
while (NCB != 0)
{
FillPin <: AllZeroes;
ClearPin <: AllOnes;
NCB = NCB -1;
}
ClearPin <: ClearBits2;
FillPin <: AllZeroes;
sync(ClearPin);
}
[/color][/size]
[code] FillPin <: AllOnes;
0x00010174 <FillClearPulse+200>: ldwdp (lru6) r2, dp
0x00010178 <FillClearPulse+204>: out (r2r) res[r2], r11
ClearPin <: AllZeroes;
0x0001017a <FillClearPulse+206>: ldwdp (lru6) r2, dp
0x0001017e <FillClearPulse+210>: out (r2r) res[r2], r3
NFB = NFB - 1;
0x00010180 <FillClearPulse+212>: sub (2rus) r1, r1, i 0x1
start_clock(clk);
0x00010182 <FillClearPulse+214>: ldwdp (lru6) r2, dp
0x00010186 <FillClearPulse+218>: setc (ru6) res[r2], i 0xf
while (NFB != 0)
0x00010188 <FillClearPulse+220>: brft (ru6) r1, i 0x2
0x0001018a <FillClearPulse+222>: brfu (u6) i 0x10
{
FillPin <: AllOnes;
0x0001018c <FillClearPulse+224>: ldwdp (lru6) r2, dp
0x00010190 <FillClearPulse+228>: out (r2r) res[r2], r11
ClearPin <: AllZeroes;
0x00010192 <FillClearPulse+230>: ldwdp (lru6) r2, dp
0x00010196 <FillClearPulse+234>: out (r2r) res[r2], r3
NFB = NFB - 1;
0x00010198 <FillClearPulse+236>: sub (2rus) r1, r1, i 0x1
0x0001019a <FillClearPulse+238>: brbu (u6) i 0x14
}
FillPin <: FillBits;
0x0001019c <FillClearPulse+240>: ldwdp (lru6) r1, dp
0x000101a0 <FillClearPulse+244>: out (r2r) res[r1], r6
ClearPin <: ClearBits1;
0x000101a2 <FillClearPulse+246>: ldwdp (lru6) r1, dp
0x000101a6 <FillClearPulse+250>: out (r2r) res[r1], r5
while (NCB != 0)
0x000101a8 <FillClearPulse+252>: brft (ru6) r0, i 0x2
0x000101aa <FillClearPulse+254>: brfu (u6) i 0x10
{
FillPin <: AllZeroes;
0x000101ac <FillClearPulse+256>: ldwdp (lru6) r1, dp
0x000101b0 <FillClearPulse+260>: out (r2r) res[r1], r3
[/code]