4 Processor pipeline XLINK and Boot configuration

Technical discussions around xCORE processors (e.g. xcore-200 & xcore.ai).
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rp181
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4 Processor pipeline XLINK and Boot configuration

Post by rp181 »

I am designing an application that uses 4 L1-128 processors. I want to be able to be able to program this with one piece of code, defining cores like in a G4 (I Don't want to write 4 different programs). To do this, I did the following:

JTAG: TMS, TCK, TRST, and RST in parallel. TDI enters node zero, TDO of node zero goes to TDI of node 1, etc.. and TDO of node 3 is used as TDO.

Boot: Here is one of my questions. Do I need to boot from XLinks to program it as one system, or can I configure them all to boot from flash on the mode pins (Can this be reconfigured in the XN?). I see that the XK-1A has both mode pins tied to TRST, so it is set to boot from flash, but documentation hints that boot from links is needed.
I also recently fabbed a single processor board for an IMU, with both mode pins tied to TRST_N. When running an application on it without flashing, XDE gives me a warning that the mode pins are not configured to boot from JTAG. Why is this happening? TRST is supposed to be pulled low at boot by the XTAG, thus booting into JTAG mode (even if this didn't happen, how is it running the application?)

Xlinks: How do I connect these? I am using Link B as the upstream link, and C or D for the downstream one. Do I connect:
1o<->1o[D]
0o<->0o[D]
0i<->0i[D]
1i<->1i[D]
or:
1o->1i[D]
0o->0i[D]
0i<-0o[D]
1i<-1o[D]

The second makes logical sense to me, but from what I am interpreting, XK-1A does the first.
Thank you!


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segher
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Post by segher »

rp181 wrote:I am designing an application that uses 4 L1-128 processors. I want to be able to be able to program this with one piece of code, defining cores like in a G4 (I Don't want to write 4 different programs).
This means you want to use a single SPI ROM, and boot the other three
chips via their xlinks.
To do this, I did the following:

JTAG: TMS, TCK, TRST, and RST in parallel. TDI enters node zero, TDO of node zero goes to TDI of node 1, etc.. and TDO of node 3 is used as TDO.
That is all fine. You probably want some buffers on at least TMS etc.
Boot: Here is one of my questions. Do I need to boot from XLinks to program it as one system,
You are building one application, not four; the tools expect to store that
in one SPI ROM; you have to boot the other three cores via their link B.
or can I configure them all to boot from flash on the mode pins (Can this be reconfigured in the XN?).
The cores cannot "see" anything in your XN (configured by it, really) until
they have booted!
I also recently fabbed a single processor board for an IMU, with both mode pins tied to TRST_N. When running an application on it without flashing, XDE gives me a warning that the mode pins are not configured to boot from JTAG. Why is this happening?
It sounds like you got something in the circuit wrong. Can you show the
relevant schematics?
TRST is supposed to be pulled low at boot by the XTAG, thus booting into JTAG mode (even if this didn't happen, how is it running the application?)
The mode pins are sampled by the core at the time RST is released. To
boot into "JTAG mode" (which really is "do not boot"), the tools keep TRST
asserted while releasing RST, and on the board asserted TRST is set up
to pull the mode pins low.

The tools use this to get a clean and well-defined state of the chip before
loading an image and starting it. If you run an image without putting the
chip into such a clean state first, odd things can happen because various
resources are in unknown states, and the initialisation in your image will
generally not work with just any state either. But in many cases it will still
work; do not be surprised if you see some gremlins though.
Xlinks: How do I connect these? I am using Link B as the upstream link, and C or D for the downstream one.
It sounds like you have it right, but to make sure: link B on all devices
that boot from link should face towards the device with the SPI.

You connect in to out, never in to in or out to out.
The second makes logical sense to me, but from what I am interpreting, XK-1A does the first.
XK-1A only contains one device, you probably mean how it connects to
the XSYS connectors, which can be a bit confusing (is there an actual
specification for XSYS btw? I can't find it).

Here is a doc you should definitely look at: http://www.xmos.com/published/xs1-l-lin ... guidelines

Good luck have fun,


Segher
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Bianco
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Post by Bianco »

When running an application on it without flashing, XDE gives me a warning that the mode pins are not configured to boot from JTAG. Why is this happening? TRST is supposed to be pulled low at boot by the XTAG, thus booting into JTAG mode (even if this didn't happen, how is it running the application?)
Sounds like your RESET is malfunctioning. Given that TRST indeed pulls the mode pins right, one sees this behaviour when the XTAG2 is unable to get the device in reset, for example when the RESET of the XTAG2 is not connected to the target device at all.

If you would generate a PDF of the schematics of your eagle files, we could take a look.
I don't bother with eagle files :-)
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Post by rp181 »

Thank you for the replies.
I will go scope the JTAG signals now and see what is going on with TRST and RST. I attached the schematic, and here is the picture of board layout with TRST_N highlighted.


The XK-1A has both mode pins tied to TRST. Doesn't this mean it will boot into flash, even when multiple XK-1A's are connected? Or does the XK-1A not support the write one piece of code thing?

I have buffers (one for each processor, I patterned the same template 4 times) on RST, TCK, TMS, and TRST with pull ups on TRST and DEBUG (Not used). Actually, maybe this the problem. Sometimes different resistors find their way into other boxes, I will check that.

I will trace the XK-1A connectors out again, I really don't want to get a 10 layer board wrong!
140mm x 114mm, 64 analog inputs and 32 analog outputs.


Bianco: Out of curiosity, what software do you use for PCB's? I looked around when I was buying, and settled on Eagle.
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Post by Bianco »

I'm using Altium Designer for my boards, It's not free and quite expensive but it's pretty good.

You don't need a capacitor on the TRST_N line (C26), the sooner you pull it up the better.
I have my concerns about whether the XTAG2 has problems with the 100nF on the RST_N line (C27), it might take too long to discharge it. In any case i can recommend to use a real power-on-reset generator such as the TPS3808G09
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Post by rp181 »

I took those capacitors off, and powered on the board (no JTAG). It seems that the RST line is pulling high before the core supply comes online, and the capacitor doesn't really help at all.

If I use that power on reset chip, do I need the pullup resistor on the RST line? Also, can I just put one of those for all the processors (Since RST is buffered), and keep it how it is in the schematic (I just wouldn't populate the capacitors)?
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Post by Bianco »

I added a few examples in the attachment.
In each case an OR function is performed in such a way that there will not be multiple driven lines.

Do not connect the XTAG2 RESET line to the TPS3808G09 Master Reset input. There will be a delay after the master reset is deasserted. The duration of this delay depends on the Ct pin, but the smallest possible delay is 1,25mS which is too long.
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Post by segher »

rp181 wrote:The XK-1A has both mode pins tied to TRST. Doesn't this mean it will boot into flash, even when multiple XK-1A's are connected? Or does the XK-1A not support the write one piece of code thing?
Each board will boot from its own SPI ROM. By programming all the
slave nodes with a teeny little piece of program that does nothing
more than boot from link, you can fake it as one system.
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