New U series Chip confusion

[Folknology]

I received notification today of updates from Xmos including the exciting new U (USB) range, which linked here

However I am now getting quite mixed up about logical cores, logical processes, tiles and xCores, maybe its just been a long day but the info on that page doesn't seem very clear to me, can someone check it please for my own sanity.


**Update
Ok I have taken another look after taking a break and getting some food ;-)
Here are some more specific queries re this new series :

1) Is this new U series in addition to the previously announced SU series, or are they meant to be the same thing?
2) This new series indicates extra 'USB tiles' but doesn't indicate how many xCores are running on them is there an explanation for this as they clearly need xCores on which to run?
3) For the USB Tiles do they have their own memory space or is it shared with one or both of the other xCore tiles?
4) The text mentions U8, U10, U12 and U16 versions and shows diagrams of U8 and U12 with xCores, but the text about U10s refers to Logical processes rather than logical cores,does this mean there is something unique about the U10 threads/cores compared to the others.
5) Even though the 'UX' part coding seems to mean x xCores, the part listings below show different values (e.g. U10,12 and 16 having just 10 xCores each)
6) Given our recent reference points each tile historically had 8 logical xCores, how do we now get down to 5 or 6 logical cores, is it because the others are being used for USB tile purposes or is it a yield thing like AMD/Intel used to do with their cores/CPUs
7) Are there any concrete datasheets (or port maps) for the new UX series so we can check out the IO capability, as that is important from a design perspective, as is some ball park pricing to assess for projects.


P.S have I said how exciting these are yet...

regards
Al

[segher]

However I am now getting quite mixed up about logical cores, logical processes, tiles and xCores,

On that page, "tile" means "die".

1) Is this new U series in addition to the previously announced SU series, or are they meant to be the same thing?

In at least one place it still says SU1. They are the same thing as far as I can see;
everything matches, too.

2) This new series indicates extra 'USB tiles' but doesn't indicate how many xCores are running on them is there an explanation for this as they clearly need xCores on which to run?

USB tiles do not contain XCores. They are mixed analog/digital ICs that contain a
USB PHY, ADCs, DC-DC converters, clock generator, and whatever I forgot. You talk
to it over an XLink, presumably to some register interface. I haven't looked at the
details yet.

5) Even though the 'UX' part coding seems to mean x xCores, the part listings below show different values (e.g. U10,12 and 16 having just 10 xCores each)

I think that table is in error, and the parts really have 10, 12, 16 threads.

6) Given our recent reference points each tile historically had 8 logical xCores, how do we now get down to 5 or 6 logical cores, is it because the others are being used for USB tile purposes or is it a yield thing like AMD/Intel used to do with their cores/CPUs

Good question. A third option is that they are artificially limited, again like
on mainstream CPUs.

P.S have I said how exciting these are yet...

They look nice alright :-)

[Folknology]

However I am now getting quite mixed up about logical cores, logical processes, tiles and xCores,

On that page, "tile" means "die".

1) Is this new U series in addition to the previously announced SU series, or are they meant to be the same thing?

In at least one place it still says SU1. They are the same thing as far as I can see;
everything matches, too.

2) This new series indicates extra 'USB tiles' but doesn't indicate how many xCores are running on them is there an explanation for this as they clearly need xCores on which to run?

USB tiles do not contain XCores. They are mixed analog/digital ICs that contain a
USB PHY, ADCs, DC-DC converters, clock generator, and whatever I forgot. You talk
to it over an XLink, presumably to some register interface. I haven't looked at the
details yet.

5) Even though the 'UX' part coding seems to mean x xCores, the part listings below show different values (e.g. U10,12 and 16 having just 10 xCores each)

I think that table is in error, and the parts really have 10, 12, 16 threads.

6) Given our recent reference points each tile historically had 8 logical xCores, how do we now get down to 5 or 6 logical cores, is it because the others are being used for USB tile purposes or is it a yield thing like AMD/Intel used to do with their cores/CPUs

Good question. A third option is that they are artificially limited, again like
on mainstream CPUs.

P.S have I said how exciting these are yet...

They look nice alright :-)

Clearly this tile/die business is making things more confusing than they need be.

The diagrams clearly show channels as the interface between the USB tiles/dies and the xCore tiles/dies, or are these channels/links just using some of those xCores, i.e. do some of the 8 xCores get automatically used up with USB leaving less, same with 10,12 and 16 xCores. It would be good to see a better explanation of this as well as port maps etc.. to clarify operation


regards
Al

[Folknology]

OK I jusr re-read the latest SU1 datasheet and found the following:

11.1
Logical Core Requirements
The XMOS XUD software component runs in a single logical core with endpoint and
application cores communicating with it via a combination of channel communica-
tion and shared memory variables.
Each IN (host requests data from device) or OUT (data transferred from host to
device) endpoint requires one logical core.
To guarantee correct operation the USB logical core must run at at least 80 MIPS,
and the logical cores that communicate with the USB core must also run at 80
MIPS. This means that no more than six logical cores execute at any one time on a
500MHz device.

This provides some better clues and hints (I am assuming that the U series are the same as the SU obviously). Maybe the U8 and U16 are fastest clocking, followed by U12 and finally U10, hence the number of xCores per tile reducing (in order to maintain the USB latency reqs)

*Update this doesn't allow for tile skew whereby the tile doing USB has this issue whilst the other does not which would suggest uneven xCores per tile (not advertised). However it could suggest grading of the tiles for upper clock frequency and of course matching them when in pairs.

regards
Al

[Folknology]

Ok it looks like the page has been edited and some of the mistakes corrected (thank you guys) so the numbers of cores now add up. However there still seems to be something new now with 'logical cores' (xCores) being interchanged with 'logical processors', it would be much more clear if the page, and xcore terminology in general, could be consistent without introducing new ambiguous terms, so perhaps we should stick with logical cores (xCores)?

Is it possible to clarify the clock speed/logical core issues mentioned above so we can get an idea of what we do get with U8,10,12 and 16 devices?

I am assuming that the SU1 device mentioned previously is just a 500mips U8 (700Mips) and that everything else is the same? I also guess this means it is only capable of 6 logical cores (xCores) in order to meet the latency requirements of the USB tile, can Xmos clarify this please?

Sorry for repetition but I would also like to request portmaps, datasheet and ball park pricing from Xmos for the UX series

Really excited by the possibilities these offer..

regards
Al

[ozel]

note that they finally released the Audio 2.0 DJ Kit board, featuring the U8.
http://www.xmos.com/discover/products/x ... 2.0-dj-kit
(looks like it has two slice connectors :)
You could try to request the corresponding sw_usb_audio code, released yesterday...

[Folknology]

note that they finally released the Audio 2.0 DJ Kit board, featuring the U8.
http://www.xmos.com/discover/products/x ... 2.0-dj-kit
(looks like it has two slice connectors :)
You could try to request the corresponding sw_usb_audio code, released yesterday...

Yeah not sure how they manage 2 slices with a single U8, I expected a U1,12 or 16, it must be some funky port arrangement, or a new slice port type instead of star, triangle, square or circle. Maybe its a new Hex slice or some such, but difficult to tell as no real data for the new DJ Kit, not even a brief let alone a manual or schematic?

Xmos Can we have a datasheet,manual and or schematics for the DJ kits please, and can anyone explain the new slice type?

P.S. I have been waiting to see a UX version of Slice kit

Puzzled
Al

[Folknology]

I have just noticed one other point of confusion, the U8 is specified as having 28 I/O, but the SU part has 37 I/O in the same package, something my designs are relying on. I hope therefore this is just a typo and will be corrected shortly?

regards
Al

[ale500]

The old datasheet is still there... I hoped for a hand-solderable package for new parts, but most probably the frequency doesn't allow it :/. Are they going to drop 4 cores devices ? it seems so...

[ozel]

you mean because of the external 25Mhz oscillator or EMI aspects due to non optimal grounding?

I never thought about it that way.
Just supposed it's a question of supply and demand, where the industry prefers tiny parts over easy pin access and you can't offer every package type as a small company (esp. since the DIYers might not buy enough parts).