XLink (-L) Non-volatile Memory and I/O Service Board

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XLink (-L) Non-volatile Memory and I/O Service Board

Post by Allein »

Version: 0.1
Status: Under development
License: Custom Licence

XLink (5W) Channel Ends are implemented as a Service through a small FPGA managing both an MRAM memory chip and an I/O connector, thus serving as a non-volatile memory server for XCores.

Goals are:

1) to make a 4MB..16MB MRAM memory bank available to any XCore through an XLink Service (non-volatile magnetic RAM, 10..20ns Tacc, 20Y+ data retention, unlimited R/W)

2) to complement the internal XCore SRAM with a large and fast multi-MegaBytes non-volatile storage, allowing for data logging, data mining, near-line storage, ...

3) to support random access through data streaming on both the up- / down-XLink

4) to offer 2 XLinks (5w) for connecting the MRAM banks to multiple XCores, with two operational modes:

a) one single big data repository with one producer/consumer XLink/XCore and many XLink/XCore consumers = Dispatching Data Repositery

b) one MRAM bank per XLink / XCore = Private XCore Data Repository

5) to offer an XLink interface to an I/O connector

6) to implement this PCB following the XMOS SliceKit specification, allowing for a direct connection to the new XMOS DevKits
Targeted performance: to sustain the bandwidth offered by 5w XLink (-L) in streaming mode, i.e. 31MBps (or 250Mbps), both in read and write; to operate concurrently, at 31MBps each, with 2 XLink Services in parallel.
Project status: detailed analysis done | VHDL implementation well advanced | PCB implementation soon to be started

Project schedule: available to Beta Users sometimes in Q4''2012
Any input, idea, dream, ... are welcome in this early stage

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Post by lilltroll »

You will get 31 of 5 starts possible from me if you make this work !
Probably not the most confused programmer anymore on the XCORE forum.
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Post by Allein »

May I ask you how you'd like / dream to use it ? This may have a direct impact on the schematic - and I hate missing an option...
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Post by Gravis »

my dream is simple.
1) use super cheap FPGA (a QFP that you can actually solder by hand)
2) use SDRAM (managed by the FPGA of course)

i dont need multiple interfaces as they would really complicate things and require a beefier and more expensive FPGA.
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Post by Allein »

- cheap QFP FPGA: OK
- SDRAM: unfortunately no; we are targeting applications were non-volatility is essential. And for random access, an SRAM interface like the one offered by MRAMs (www.everspin.com) is much more efficient than SDRAM.
- multiple channels: we are definitely heading towards two versions: a light one with one XLink channel and 0.5 to 4 MB of MRAM, and a larger, multi-channel one. BTW, having multiple channels doesn't impact that much on the FPGA complexity and size.
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Post by porsche »

If there is a Xlink2Local (like PCI bus / local bus) service, that's great.
or if there is a Xlink2APB (arm bus), cool!
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Post by Carpentier »

I would be interested to know:
-how it will be power supplied (connectors , external supply)
-how it will be connected to consumer cores (what style of physical connectors).
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Post by DrNO »

Hey I noticed that the XLINK VHDL implementation is well advanced. Where exactly did you find documentation on the XLINK protocol? Or did you scope it and reverse engineer it? Think I could get a peek at your VHDL code?
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Post by MAD »

you have to love freescale/everspin MRAM you may have missed the latest news, they now do a generic 64Mbit DDR3 stick to start with.

thats probably too big here OC but you get the massive long term MRAM + Xcore potential here i assume

http://semiaccurate.com/2012/11/16/ever ... a-reality/

just as a possibility i thought id add my long time ideal you may consider when laying it out as one version for the long term benefit of everyone ...

"Be Better than everyone else, not just as good as"

assuming everspin do a small enough package its worth considering using a generic SODIMM and daughter board layout combination with several generic SODIMM slots to populate it with.

or if you wanted to get really creative for the long term make a full generic SODIMM System On Module with several Xcore directly integrated on there with the MRAM.

like these and several other ARM devs already do in the low end core counts, no QUAD cortex unfortunately yet.
http://www.karo-electronics.com/tx27.html to make it dead easy for the end consumer 3rd party dev.

need more cores, buy and plug in another SODIMM card, run out of SODIMM slots, in our case plug another xcore PCB in beside it unlike those ARM guys that replace the old daughter board with a larger one...

you see the potential of this ,its great long term and compliments the existing Xcore projects very nicely, plus potential great PR inthe wider world if anyone makes a daughter board for taking both a xcore and ARM cortex A9/A15 quad at the same time :)

then OC theres also the news that samsung just made a 64GB embedded multimedia card (eMMC) using 10nm-class process technology to also consider as another option perhaps http://www.digitimes.com/news/a20121116PR206.html
"The new 64Gb NAND memory went into production late in October 2012...."
"...sequential read and write speeds are 260 megabytes per second (MB/s) and 50MB/s respectively, which is up to 10 times faster than a class 10 external memory card that reads at 24MB/s and writes at 12MB/s, Samsung said."

but faster, infinite endurance, zero power state retention MRAM DDR3 is it for me , an least until the even faster throughput MRAM Wide IO Mobile DRAM package is made available somewhere as an option ;)

out of interest has anyone got ideas how you might interface that new up to 17GBps Wide IO 512-bit data interface spec to XCORE at a reasonable speed ?
http://www.jedec.org/news/pressreleases ... obile-dram

http://chipdesignmag.com/sld/blog/2011/ ... on-memory/
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Post by Allein »

* XLink (5w) & MRAM board:
Form factor: the first implementation will be a SliceKit slice form, with one XLink (5w), one FPGA and one or two 4Mb / 16Mb MRAMs on it (= 256kB to 4MB, depending on which and how many parts are fitted).
XLink protocol / VHDL code: will not be open-sourced in a first time; only pre-programmed FPGAs or EDIF netlists will be available. This might evolve over time.
Development status: the XLink (5w) Core coding is finished, debugging on-going. As soon as the Core is stable and validated, the PCB will be finalized.

New DDR3 64Mb MRAM parts & DIMMs: DDR3 isn't directly usable with standard CMOS I/O ports (SSTL signals), would require an - expensive - DDR3 IP-Core on a larger and more expensive FPGA... outside of my own-money budget, but quite easily feasible if someone is ready to finance it ;-)

* XCore & MRAM on SODIMM
Interesting idea, to be discussed... next year, maybe