Special floating points formats ???

Technical questions regarding the xTIMEcomposer, xSOFTip Explorer and Programming with XMOS.
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lilltroll
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Special floating points formats ???

Postby lilltroll » Wed Jan 20, 2010 6:56 am

In some cases (HIFI-Audio), IIR-filters with poles very close to the unit circles are needed togheter with a roundoff-noise SNR > 100 dB.
Example, a parametric EQ around 40 Hz with a Q-value of 15 at a fs>= 48 kHz.

Such filters are very hard to implement with any fixed point filter structures, including ladder filters.

So I implemented a floating point IIR-filter in C and connected it from XC - and it works :)

Using double, it becomes very computational heavy (of course), on the other hand - double can handle values up to ~1.8*10^308, which is not relevant for audio filtering.

Just guessing, I belive that a format with 30-32 bits of the significand togehter with 8 or 16 bits of the exponent could be optimal on XMOS. (I belive there exists special libs for the fixed point ARM family regarding special floating points)

Is there any special floating point lib. that could be reused (Single-prec. normally uses 23 bits to the significand)? Or is the emulation of single floating point already implemended in such a way that it is more accurate than the standard IEEE one?

In the document XMOS Compiler Collection version 8.7 you can read:
(§5.2.4.2.2) The accuracy of the floating-point operations and of the library
functions in <math.h> and <complex.h> that return floating-point results.
This is intentionally left undocumented.
Last edited by lilltroll on Wed Jan 20, 2010 9:06 pm, edited 1 time in total.
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JohnR
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Postby JohnR » Wed Jan 20, 2010 3:32 pm

A few days ago I found a neat single/double precision math library called SoftFloat written in standard C that I am now trying to optimise for XMOS assembly. At present, I have been testing the integer->double and double->integer functions. The XMOS assembler has some useful routines, eg CLZ for counting leading zeros - that can replace a quite long-winded function, countLeadingZeros32(), in the SoftFloat code.

John Robbins
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Folknology
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Postby Folknology » Wed Jan 20, 2010 3:47 pm

This sounds Excellent John, really handy

It would be great if you could also provide some basic benchmarking to show those enhancements, especially showing single versus double. Obviously when crunching certain floats whilst meeting external timing constraints could make this very useful indeed.
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Postby JohnR » Wed Jan 20, 2010 8:35 pm

Thanks for the reply.

I will write the first version of the FP library in XMOS assembler to handle doubles and later floats. Initially, NANs, denormals and so on will not be handled.

A year or so ago I started on modifying a 68000 FP library by Nicolas Benezan for use in XMOS devices - this used a non standard format, halfway between a normal float and a double. I had to suspend this development for other projects and when I restarted, I found SoftFloat which seemed to be a better approach.

All being well, I should have the basic math operations up and running in the next few days.

John.
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leon_heller
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Postby leon_heller » Wed Jan 20, 2010 9:07 pm

Analog Devices has a two-word floating point format that was used by their earlier 16-bit compiler: the exponent is stored in one word and the fraction in another. I used it in an application with the newer compiler because IEEE was far too slow. Here is the code I used for addition:

Code: Select all

/*

============================================================================================

	ADI two-word floating-point routines

        Floating-Point Addition
                z = x + y

        Calling Parameters
                AX0 = Exponent of x
                AX1 = Fraction of x
                AY0 = Exponent of y
                AY1 = Fraction of y

        Return Values
                AR = Exponent of z
                SR1 = Fraction of z

        Altered Registers
                AX0,AY1,AY0,AF,AR,SI,SE,SR 
                
        Computation Time
                11 cycles

============================================================================================ */

fpa:    AF=AX0-AY0;		{Is Ex > Ey?}
        IF GT JUMP shifty_1;	{Yes, shift y}
        SI=AX1, AR=PASS AF;	{No, shift x}
        SE=AR;
        SR=ASHIFT SI (HI);
        JUMP add;
shifty_1: SI=AY1, AR=-AF;
        SE=AR;
        SR=ASHIFT SI (HI), AY1=AX1;
        AY0=AX0;
add:    AR=SR1+AY1;		{Add fractional parts}
        SE=EXP AR (HIX);
        AX0=SE, SR=NORM AR (HI);{Normalize}
        AR= AX0+AY0;		{Compute exponent}
        RTS;
Similar routines might be useful for speeding up XMOS arithmetic.

Leon
Last edited by leon_heller on Wed Jan 20, 2010 9:10 pm, edited 1 time in total.
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lilltroll
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Postby lilltroll » Wed Jan 20, 2010 9:08 pm

I earlier found this with help by google:
http://old.nabble.com/XMOS-using-LLVM-td19980703.html
and "Richard Osborne-4" even wrote in the forum today regarding the libs.

What is the difference by your work, you will optimize it in ASM for XMOS !?
(As I understand it, the math.h for XMOS is already based on Soft Floats, but looking at the simulation trace you see that it eats instructions, and makes alot of pack and unpack)
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lilltroll
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Postby lilltroll » Wed Jan 20, 2010 9:22 pm

Here is my results from a "non at all optimised" code:

With a floating point BiQuad section in one thread, I can run 6 threads in total on one core, filtering audio at 48 kHz thrue the BiQuad section.

At seven treads in parrallell I believe that the BiQuad secion is starved out of time. The BiQuad section uses 5 floating point multiplications and 4 floating point add or sub and 2 casts.
I guess that would give me an efficient kFLOPS at 432 @ 66 MHz thread speed."
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lilltroll
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Postby lilltroll » Wed Jan 20, 2010 9:26 pm

leon_heller wrote: Similar routines might be useful for speeding up XMOS arithmetic.

Leon
I guess they really would, since the SoftFloats seems to use > 100 instructions per FLOP.

First alot of unpack, thereafter the actual math, finally alot of pack.

Something fast that supported Multiplication and Add would be nice for filtering!
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JohnR
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Postby JohnR » Thu Jan 21, 2010 2:43 am

There seems to be some confusion re "SoftFloat" - in my post I was referring to a library written by J Hauser not soft-float as found in gcc.

Leon - thanks for the reference - I had found it some months ago but not looked at it carefully but will do so now. By the way, are there any news groups you don't contribute to?!!.

Unlike many processors, the XMOS architecture does not include a condition register, the effect of which seems to make code more verbose.

John.
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lilltroll
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Postby lilltroll » Thu Jan 21, 2010 8:08 am

Thank you for the info John, making things clearer for me! I always appreciate to be corrected if I'm wrong, to be able to learn more.

Actually I found the J Hauser lib. when i searched the net, so I was reading that code, but couldn't understand why the XMOS simulation trace looked the way it looked.

I will try to make something similair to what leon showed with a special float format. Good practice for me, but I'm not used to ASM like you guys. But I started to do some MATLAB simulation of it.

John: Will you start a XCORE-project of your work and make it available or will it be a closed one?

Leon: Do you have some Multiplication code as well that I can take a look at?
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