FNOP

Technical questions regarding the xTIMEcomposer, xSOFTip Explorer and Programming with XMOS.
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lilltroll
XCore Expert
Posts: 955
Joined: Fri Dec 11, 2009 3:53 am
Location: Sweden, Eskilstuna

FNOP

Postby lilltroll » Thu Feb 04, 2010 5:58 pm

I am running XTA to check the performance, and in some places FNOPs happends.

XC:

Code: Select all

		lz=clz(x);if(lz<2) lz=0; else x<<=(lz-1);ye=B0e-lz;TEMP=ye-Z0e;
		l=0;{h,l}=macs(x,B0,h,l);

Code: Select all

                     0x10216 	neg (2r) r8, r0
                     0x10218 	sub (2rus) r6, r8, i 0x0
                     0x1021a 	add (2rus) r2, r4, i 0x0
                     0x1021c 	add (2rus) r0, r4, i 0x0
                     0x1021e 	ldwcp (lru6) r11, cp[i 0x10]
                     FNOP
                     0x10222 	maccs (l4r) r2, r0, r9, r11
In this case, it allocates the registers used for the maccs, just before the maccs instruction. If the LoadWord happend earlier, could I write the code without FNOP?
It´s something with the pipeline, isn't it?
(The 8-bit "computer" we made by hand from scratch in the university didn't have a pipeline - but it had 8 LEDs and 8 on-off switches+1 switch for the clock. After programming it for 3 h with the switches, it could calculate 4+7, showing the results with the LEDs)
Probably not the most confused programmer anymore on the XCORE forum.
richard
Respected Member
Posts: 318
Joined: Tue Dec 15, 2009 12:46 am

Postby richard » Thu Feb 04, 2010 6:27 pm

If the instructions were rearranged into the following sequence there would be no FNOP:

Code: Select all

neg r8, r0
sub r6, r8, i 0x0
ldwcp r11, cp[i 0x10]
add r2, r4, i 0x0
add r0, r4, i 0x0
maccs r2, r0, r9, r11
You get a FNOP when the next instruction isn't in the instruction buffer. Take a look at the section 5.1 Scheduler Implementation in the The XMOS XS1 Architecture book for details.

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