change output falling edge to rising

Technical questions regarding the xTIMEcomposer, xSOFTip Explorer and Programming with XMOS.
ENGHK
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change output falling edge to rising

Postby ENGHK » Tue Mar 02, 2010 10:21 am

is there any function that I can make the output port to be sampled by rising edge rather than the falling edge ?
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Woody
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Postby Woody » Tue Mar 02, 2010 11:48 am

Are you clocking the port off a clock block driven from an external port pin?
richard
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Postby richard » Tue Mar 02, 2010 12:37 pm

Assuming the port is clocked off a clock block driven from an external port pin the you can invert the 1-bit port used as a clock source. Use the set_port_inv() function from xs1.h. Inverting the clock source has the effect of swapping the rising and falling edges of the clock.
ENGHK
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Postby ENGHK » Wed Mar 03, 2010 2:19 am

yes, i am using external clock. But once i use set_port_inv(INCLK) (INCLK is the input port from the clock). Although the clock is inverted, i.e. 0 becomes 1 and 1 becomes 0, I still get a wrong output. Please see the attached photos.

What my output I want is 0x12AB56D4.
i.e. 0001 0010 1010 1011 0101 0110 1101 0100

The first one is the output using falling edge. But my device counts as rising edge and so the output is 15B56AA4. It is correct if we count the falling edge in this photo and will get the result right.

The second one is the output after using set_port_inv. The result is quite near to what I want. However, the result is 0x1B6Ad548.

i.e. 0001 1011 0110 1010 1101 0101 0100 1000

It is the reverse of 0x12AB56D4. But the first 0001 is wrong. What's the problem?
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ENGHK
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Postby ENGHK » Wed Mar 03, 2010 5:55 am

another question, how can I make the data1 line to be put 1 cycle before ?

make from output 3.JPG to output 4.JPG
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