Problem at first load with JTAG
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norman
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what is your appreciation of "very quickly " for "1v0 doesn't come up very quickly after the 3v3" ? thanks
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Redeye
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Well, 100ms is too much from our experiments. The testing wasn't exhaustive because this wasn't the problem we were looking for, but it seems to need to be no more than a few milliseconds.norman wrote:what is your appreciation of "very quickly " for "1v0 doesn't come up very quickly after the 3v3" ? thanks
I'm just curious as to why this is and/or where it's specified in the datasheets because if there's a maximum delay for reliable booting then surely it should be stated? If it is then I've missed it but happy to be corrected.
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mon2
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Norman - would you be able to share the similar scope capture for the 3v3 and 1v0 lines from the working XMOS board ? The delay between the power rail sequencing appears to be too long at 500 ms. I would have expected this value to be much smaller.
Most datasheets will list a max time between power rails if such sequencing is required. Don't believe we have seen this value in the datasheets either but we have also shadowed the referenced designs to be safe. Perhaps XMOS can chime in on this topic to define a max value for this (important) delay. It appears this delay can't be too long nor too short but just right :)
A suggestion is to source a 1v0 power supply controller which features an enable pin and stitch into place to replace the LDO. Also to lower the amount of bulk capacitance from the PCB. There is a lot of bulk capacitance before and after the 1v0 LDO. Such high capacitance can lead to in-rush current issues which is another headache.
https://en.wikipedia.org/wiki/Pre-charge
http://www.murata.com/en-global/product ... 0121029-p1
In staring at the posted schematic, the power sequencing effort looks ok for the reset line but as Redeye is observing the power rail delays need attention.
Power supply sequencing is often used to prevent latch-up conditions.
Most datasheets will list a max time between power rails if such sequencing is required. Don't believe we have seen this value in the datasheets either but we have also shadowed the referenced designs to be safe. Perhaps XMOS can chime in on this topic to define a max value for this (important) delay. It appears this delay can't be too long nor too short but just right :)
A suggestion is to source a 1v0 power supply controller which features an enable pin and stitch into place to replace the LDO. Also to lower the amount of bulk capacitance from the PCB. There is a lot of bulk capacitance before and after the 1v0 LDO. Such high capacitance can lead to in-rush current issues which is another headache.
https://en.wikipedia.org/wiki/Pre-charge
http://www.murata.com/en-global/product ... 0121029-p1
In staring at the posted schematic, the power sequencing effort looks ok for the reset line but as Redeye is observing the power rail delays need attention.
Power supply sequencing is often used to prevent latch-up conditions.
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mon2
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Norman, try the following - since you likely will not have access to another regulator today, try to mod your design as follows:
a) remove the bulk caps on the input and output of the LDO.
b) replace with lower cap values of say 10uf to 47uf
c) then monitor the same 3V3 and 1V0 delays till you fall into the delay range noted by Redeye. Play with the cap values till you are in spec. Not the recommended approach for a production unit but should be fine for your lab testing.
Effectively, you are creating a hacked version of the power sequencer but without the enable pin (which is missing on your LDO). The voltage monitors will still properly reset your CPU after both the 3v3 and 1v0 are stable.
Something to try while waiting for other power supply options.
The JTAG TMS spikes look nasty - do you see the same and same width on the working XMOS board ?
The power supply we will be using for the 1v0 rail (with enable) is the following device from ROHM:
http://www.digikey.com/product-detail/e ... ND/3693228
http://www.rohm.com/web/global/distribu ... 2/sample/0
Once you have your power supply sequence delays in order, we can rule out this issue as the root cause and move on. Some purists will argue against the idea of using a switching power supply for high end audio (due to switching electrical noise / EMI) but our line of work is not in this field so proceed accordingly.
a) remove the bulk caps on the input and output of the LDO.
b) replace with lower cap values of say 10uf to 47uf
c) then monitor the same 3V3 and 1V0 delays till you fall into the delay range noted by Redeye. Play with the cap values till you are in spec. Not the recommended approach for a production unit but should be fine for your lab testing.
Effectively, you are creating a hacked version of the power sequencer but without the enable pin (which is missing on your LDO). The voltage monitors will still properly reset your CPU after both the 3v3 and 1v0 are stable.
Something to try while waiting for other power supply options.
The JTAG TMS spikes look nasty - do you see the same and same width on the working XMOS board ?
The power supply we will be using for the 1v0 rail (with enable) is the following device from ROHM:
http://www.digikey.com/product-detail/e ... ND/3693228
http://www.rohm.com/web/global/distribu ... 2/sample/0
Once you have your power supply sequence delays in order, we can rule out this issue as the root cause and move on. Some purists will argue against the idea of using a switching power supply for high end audio (due to switching electrical noise / EMI) but our line of work is not in this field so proceed accordingly.
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norman
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this is what i got at power up with 3V3 and 1V on the XR-AVB-LC-BRDmon2 wrote:Norman - would you be able to share the similar scope capture for the 3v3 and 1v0 lines from the working XMOS board ? The delay between the power rail sequencing appears to be too long at 500 ms. I would have expected this value to be much smaller.
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mon2
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A quick observation is on the nice vertical rise of the working board vs. the non-working board which has a slight ramp up delay. Suspecting due to the bulk caps on the respective voltage rails.
Grab that soldering iron (which never is shut off) and pull-off some of those caps to see if the condition improves.
Grab that soldering iron (which never is shut off) and pull-off some of those caps to see if the condition improves.
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mon2
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A quick observation is on the nice vertical rise of the working board vs. the non-working board which has a slight ramp up delay. Suspecting due to the bulk caps on the respective voltage rails.
Grab that soldering iron (which never is shut off) and pull-off some of those caps to see if the condition improves.
Grab that soldering iron (which never is shut off) and pull-off some of those caps to see if the condition improves.
You do not have the required permissions to view the files attached to this post.
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mon2
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Believe we may have figured it out. Before opening the non-alcoholic beverages and your best dark chocolates...please confirm and test...
(drumroll please)...
your Mode0 & Mode1 pins are incorrectly strapped. The logic values are reversed for the 25 mhz clock source.
Mode0 = should be 0 (low)
Mode1 = should be 1 (high)
Hope this fixes the issue. Crossing our fingers...
(drumroll please)...
your Mode0 & Mode1 pins are incorrectly strapped. The logic values are reversed for the 25 mhz clock source.
Mode0 = should be 0 (low)
Mode1 = should be 1 (high)
Hope this fixes the issue. Crossing our fingers...
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mon2
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Not sure but found some possible typos in the PLL / clock tables across documents.
The tables do not match for the clock ranges nor the PLL ranges yet the settings are the same. Strange...
Please see attached. Will contact our local FAE to receive some feedback on this topic.
In theory, if you cannot change the MODE0 & MODE1 strapping due to PCB layout, you could consider to alter the external clock source to match the strapping which you have in place now. Just a thought.
The tables do not match for the clock ranges nor the PLL ranges yet the settings are the same. Strange...
Please see attached. Will contact our local FAE to receive some feedback on this topic.
In theory, if you cannot change the MODE0 & MODE1 strapping due to PCB layout, you could consider to alter the external clock source to match the strapping which you have in place now. Just a thought.
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norman
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thank you for those informations, i will try to change the oscillator as soon as possible, indeed, i can change the layout for mode0-1.
I draw my schematic from the XR-AVB-LC-BRD schematic so if it's work, i don't understand how the AVB board can work.
by the way, i start to remove bulk capacitor, and try a quick test after each one removed without success. keep going ! thanks again !
I draw my schematic from the XR-AVB-LC-BRD schematic so if it's work, i don't understand how the AVB board can work.
by the way, i start to remove bulk capacitor, and try a quick test after each one removed without success. keep going ! thanks again !