FreeRTOS Symmetric Multiprocessing (SMP) for xCORE

Technical questions regarding the xTIMEcomposer, xSOFTip Explorer and Programming with XMOS.
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FreeRTOS Symmetric Multiprocessing (SMP) for xCORE

Post by aclassifier »

I discovered this (on Linkedin): “Introducing the FreeRTOS Symmetric Multiprocessing (SMP) Github Branch” [1].

I have not found any explanation on Github about the architecture of SMP on the xCORE and what it might imply. Here is a list of some points which I would however not know the relevance of:

Now, is one SMP processor unit:
  • Several XMOS processors and external bus to shared memory?
  • Several xCORE tiles which have shared memory with.. (on the xCORE architecture on-chip tiles are connected via the xConnect switch which may also be used when communicating with off-chip tiles on other XMOS processors. The xConnect also does hw routing of packet switched data, in several topologies). But SMP at this level?
  • Several xCORE cores which already have shared memory with those on the same tile?
  • The architecture and xC already does this per tile = SMP (cores). I think this change is in the FreeRTOS kernel only.
[1] Introducing the FreeRTOS Symmetric Multiprocessing (SMP) Github Branch, by Lucio Di Jasio on 30 Jun 2021, see ... ranch.html. The github branch is at

Øyvind Teig
Trondheim (Norway)