SPDIF Receiver Project

[patw]

Hi,

I would like to add a SPDIF receiver to the USB Audio 2.0 design and the ipod dock design.

However, when looking at the SPDIF receiver module provided on the XMOS site:

https://www.xmos.com/applications/audio ... f-receiver

I can't understand how it works, how it detect different SPDIF sampling rates etc., can some one help me.

Many Thanks,

Pat

[paul]

The big thing to understand is that it is basically one giant state machine (contained in t.s).

With a little bit of reading of the architecture manual (see https://www.xmos.com/published/xmos-xs1-architecture-0) it should become fairly obvious as to how it works.

The way that clock recover works is that the state machine works out if the data it is getting is too fast or slow and then adjusts accordingly.

Cheers,

[lilltroll]

There is also other things to consider. There exist standards about how jiitered and noisy signal the receiver should be able to decode. With help of PLL and stuff (adaptive clock recovery), it has to recover a stable clock, since everything is sent in one cable.

Cirrus
http://www.cirrus.com/en/products/inter ... rters.html

http://www.wolfsonmicro.com/products/sp ... nsceivers/

Jitter in S/PDIF as wolfson describes it:
http://www.wolfsonmicro.com/documents/u ... eivers.pdf

My Conclusion for professional Audio: Skip the buttons and use the 2 1-bit ports as I2C instead, change to a CODEC with integrated S/PDIF transceiver. Use I2C to speak with the CODECs registers. Do not run the CODEC in stand alone mode.

(S/PDIF is a an almost magical stupid protocol to f*ck up a digital transmission over a 0.5m long cable at a very low bitrate ;) )

[patw]

Thank for the reply.

>change to a CODEC with integrated S/PDIF transceiver.

Do you mean that it is not a good idea to use XMOS-L1 as the SPDIF receiver? A separate chip should be use, say WM8805?

If we can use the XMOS as the SPDIF receiver then it save us a bit of cost.

Many thanks,

Pat

[lilltroll]

I guess it depends on what you are going to do with the signal. If you want to write it to file/send it to the PC over USB, the clocksignal itself is not of no interest, only the actual databits.
Even if the SPDIF signal has god SNR, consider this.

If you want to use the card as a SPDIF-> DAC, then you have to create a clock-signal to the DAC.
Suppose you would use the XMOS as clock generator, then your clock would be re-sampled to 100 MHz (or 125) that would mean jitter in the order of 10 ns.
If you would use the onboard clock-chips, those clock would skew in reference to the SPDIF clock, since they aren't ideal. Without a clock-syntesizer (or a PLL) it's nothing you can do about that, either you will collect more data than you transmit or vice versa.
To just through away a bit every now and when or insert one will create glitches.
SPDIF is one way communication. It's not like a duplex link where you can request more data.

The absolute worst with any closed loop digital control system controlling real world signal is the poor close loop freq response. You cannot replace an analogue high bandwidth closed loop with a digital control system. (Forward system as with digital channel equalisers in communication system is much easier.)