Simple USB DAC Design

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braddrew0
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Re: Simple USB DAC Design

Postby braddrew0 » Tue Sep 17, 2019 11:19 am

That's great, thanks - I completely misread that. Re-reading now, if I tie a 24.576MHz oscillator to the MCLK line (between XMOS and DAC) I can cycle between 48/96/192kHz by changing the PLL divide on the XMOS, and making sure the DAC is configured correctly for the rate (max 192kHz)?

I'll change the I2C to be 1-bit ports - I assume there's no issues with an LED or the SMUTE/PDN signals being on a multibit port? They will all have very low update rates - can always just logical and the output?

Thanks again, I appreciate the help :)

EDIT: Sorry small change - I don't mean tie the oscillator to the MCLK line, I meant feed it into a 1-bit port and then run a clockgen core to generate the MCLK signal.

EDIT2: Now I'm confused - maybe I should just tie it to the MCLK line?
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mon2
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Postby mon2 » Tue Sep 17, 2019 11:14 pm

Hi. See page # 2 of this thread:

viewtopic.php?f=7&t=4599&start=10

Digikey webpage for this pre-programmed PLL:

https://www.digikey.com/product-detail/ ... ND/5799560

there are details on the Silabs Si5351A which was factory programmed for XMOS projects. So if you search for the full p/n as shown on this thread, you can source through Digikey and Mouser the pre-programmed PLL that upon power up will output the listed clocks on the respective PLL pins. If the values are not suitable for your project, you can alter the values to suit using the I2C interface (XMOS could be the I2C bus master). It is very simple to use this PLL and should offer the desired clocks for your audio project.

This PLL is common to assorted XMOS reference designs.

One thing to keep in mind is that the XMOS CPU clock is often from this PLL. For this reason, be careful on which clocks are being modified so that you do not halt the clock which would then result in a deadlock event on the CPU that is dependent on a working clock. Sort of did this on a FPGA design a few minutes ago :)
braddrew0
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Postby braddrew0 » Wed Sep 18, 2019 7:44 am

Thanks! Just to confirm - I don't need to further divide the clock before putting it on the MCLK line, right?
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mon2
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Postby mon2 » Wed Sep 18, 2019 12:00 pm

Hi.

1) Yes, MCLK is to be used @ 24 Mhz through CLK1 on this PLL to run your XMOS CPU.

2) The other 2 clocks are to be defined at run time to support your audio rates over I2C interface. Respectively, you will need to insert I2C component in your IP to dial up the required clock value for your ADC / DAC devices.

See the last post here:

viewtopic.php?t=5099

The Si5351A is a very simple PLL that can be used to dial up any clock value with precision.

We have posted the full source code to program this PLL here:

viewtopic.php?t=4647&start=10
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mon2
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Postby mon2 » Wed Sep 18, 2019 12:09 pm

Wish to stress again that when you are adjusting the PLL clock values on CLK0 / CLK2, you cannot interrupt the value on CLK1 = MCLK = 24 Mhz else you will lock the CPU.

Respectively, for this reason, an idea is to install a dedicated 24 Mhz clock oscillator which are typically < $ 0.30 USD from Asia (3.2 x 2.5 mm @ 3v3). The 24 Mhz clock or multiple of is required for the proper USB interface framing. This clock oscillator could even be MEMS or silicon based so that your design could even be dropped without damage to the clock oscillator(s).

Then use a 25 Mhz crystal (cannot be an oscillator) on the Si5351A PLL and proceed to dial up the audio clocks as you wish, risk free since the MCLK is fixed and independent of the PLL.
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akp
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Postby akp » Wed Sep 18, 2019 12:29 pm

I wonder if the OP means MCLK is for the DAC chip itself. In that case he would want MCLK to be 24.576 MHz as posted above (assuming the DAC chip can use this MCLK, I didn't look deeply at it). Then one can do an integer clock divide on the XMOS MCU to get the correct frequencies for I2S bit clock for 48 / 96 / 192 kHz. Assuming this is CLK0 from the PLL chip you might be able to reprogram it at run time to 22.579 MHz achieve 44.1 kHz families, I don't know.

The other PLL output -- CLK1 I guess -- one wouldn't modify (per @mon2) as it's the 24.000 MHz clock for the XMOS MCU core PLL and USB interface. I would call that something like CPUCLK for instance.
braddrew0
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Postby braddrew0 » Thu Sep 19, 2019 9:48 am

Hi akp - that's exactly what I was trying to say, thanks! AKM can handle up to 192kHz with 24.576 as above. I already have a 24Mhz clock - very happy not to mess with this one :)

Thanks guys, appreciate all the help, I'll report back in once I've built and tested it! :)
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Wavelength
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Postby Wavelength » Mon Sep 23, 2019 10:18 pm

You might want to add resistors to ground on your output of the cap coupled on the audio board. That way you won't get a pop when you plug into the board. Use something like a 1M to ground after the 0.1uF. Also that's a little on the low side, you may want to use like 3.3uF, good film ones.

On the I2S from the XU208 you should have resistors especially if this is board to board like 33-47 ohms thin film work best SMD only.

Then everything above!
If you are expecting to do like 384KHz on the USB you may have some issues with multi board solutions. 24/192 is ok, above that is sometimes an issue.

Thanks,
Gordon
Wavelength Audio, ltd.

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