Multiple SPDIF receiver to I2S

Sub forums for various specialist XMOS applications. e.g. USB audio, motor control and robotics.
fabriceo
Junior Member
Posts: 6
Joined: Mon Jan 08, 2018 4:14 pm

Multiple SPDIF receiver to I2S

Postby fabriceo » Sat Dec 22, 2018 9:40 am

Hi Guys,
Can someone help me to finalize my HW design by confirming feasibility of the following project ? also a first guidance on the application would be appreciated, just as a confirmation of feasibility and to sense the level of software headach to come :)

I m in the process of designing a multichannel dac board integrating XUF208 and I d like to manage 4 SPDIF receiver, as typically coming out of a player like OPPO-203 with Vanity 203 HD board. In this context the 4 SPDIF signals are synchronized together and generated from a single 44/48k or 88/96 master clock in the player.

The design includes a fractional PLL for generating a proper I2S synch clock, and the xmos will be configured as a single I2S slave channel in TDM8 mode.
the bit clock (11/12/22/24mhz) and the master clock (22/24mhz) are generated from the PLL. The TDM frame clock is generated by a logic divider.

here is a high level diagram of the configuration,
HLD multi spdif.png
(41.27 KiB) Not downloaded yet
HLD multi spdif.png
(41.27 KiB) Not downloaded yet


and the foreseen 1bit port mapping.
XUF208 pin map.png
(76.15 KiB) Not downloaded yet
XUF208 pin map.png
(76.15 KiB) Not downloaded yet


I have possibly a spare port (QSP_CLK / P1C0) that coud generate a reference clock for the PLL but I think it is not needed as the ClockGen.xc can calculate the value for the fractional PLL and send them over I2C right ?

Also I understood from other posts that the MCLOCK is not needed for the standard I2S_lib if we do not use XUD/USB right ?

I ve read many xmos application note and source code, including the famous AN00231_ASRC_SPDIF_TO_DAC. this all is inspiring but quite complex.

Many thanks for supporting our creativity!

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