How to get started with startKIT

All technical discussions and projects around startKIT
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pstnotpd
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Re: How to get started with startKIT

Postby pstnotpd » Mon Jan 06, 2014 11:41 am

Bianco wrote:It would be misleading to advertise it as a 16-core device while 8 of them are not (trivially) usable to the programmer.
As I'd like to have a go at connecting a bunch of startkits together I'm definitely interested in how to "free up" the hidden tile. I assume if configured correctly it should be possible to only use 1 startkit as a debugger and then configure other connected startkits as 2 tile devices.
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Folknology
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Postby Folknology » Mon Jan 06, 2014 2:03 pm

pstnotpd wrote:
Bianco wrote:It would be misleading to advertise it as a 16-core device while 8 of them are not (trivially) usable to the programmer.
As I'd like to have a go at connecting a bunch of startkits together I'm definitely interested in how to "free up" the hidden tile. I assume if configured correctly it should be possible to only use 1 startkit as a debugger and then configure other connected startkits as 2 tile devices.
That sounds like an entirely new thread to me..

P.S. also see this thread

regards
Al
mhelin
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Postby mhelin » Tue Jan 07, 2014 9:30 pm

linuxguru wrote:
Phrewfuf wrote:Damn, there goes my plan on building an audio device :(
Same initial reaction as mine - BTW, you can still do a 24/192 S/PDIF to I2S converter with a StartKit, and use it to drive an external WM8727 or ES9023 DAC - it needs just 1 input and 4 outputs.
I'm quite positive that you can use startKIT as an USB audio device. It may require some changes to existing code, and as there are only four 1-bit port mapped to outside world (excluding TP1 JTAG port) you just can't do full-duplex board, or maybe can if rewrite the USB audio stack not to use MCLK in slave mode (it's needed for something, I guess for sending feedback in asynchronous mode implementation). There are also some converters which don't use bit clock (generate it internally), and I can guess xCORE I2S can generate bit clock internally if needed.

Anyway, the idea of using single startKIT as debugger and another as 2-tile device doesn't work unless you first load some application to the second one using USB. The OTP ROM bootloader makes the USB the only choice for loading data (debugger or your own code) into any tile[0] (debug tile) in bootup.
thradtke
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Postby thradtke » Wed Jan 08, 2014 1:03 pm

Phrewfuf wrote:Just played around with mine after solving the issue of a non-running IDE (Error messages are apparently hard to implement, just as decent executables instead of .bat files).
How did you solve it? I'm trying to get the Composer running on a Vista Business 64bit system to no avail. Drivers are installed and the board is correctly identified when connected.

Thanks,

Thomas
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Bianco
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Postby Bianco » Wed Jan 08, 2014 3:18 pm

thradtke wrote:
Phrewfuf wrote:Just played around with mine after solving the issue of a non-running IDE (Error messages are apparently hard to implement, just as decent executables instead of .bat files).
How did you solve it? I'm trying to get the Composer running on a Vista Business 64bit system to no avail. Drivers are installed and the board is correctly identified when connected.

Thanks,

Thomas
32-bit JRE?
thradtke
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Postby thradtke » Wed Jan 08, 2014 3:36 pm

Bianco wrote:32-bit JRE?
Yes, it's actually missing. Somehow I misread the text, concluding the 32-Bit JRE was contained.

Thanks!
mhelin
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Postby mhelin » Wed Jan 15, 2014 4:53 pm

Got the USB Audio 2.0 reference desing built and working on startKIT. The clocks on scope look noisy as hell except for the MCLK which is generated by it's own oscillator (used 12.288 MHz one, 44.1k MP3s sound a little bit funny), why is that btw.? Too bad there is no other way to load the image than the USB dynamic loading (http://www.xmos.com/download/public/Dyn ... -XTAG2.pdf), it though works fine on the PC. There aren't too many ports available either. Not very useful application for startKIT, but it can definitely be done (but then you can't use the debugger, and the other core just boots with whatever is flashed to eeprom, flashing LED's - well someone might be able to sync them with the music played through USB).
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fosfor
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Postby fosfor » Wed Jan 15, 2014 7:06 pm

mhelin wrote:Got the USB Audio 2.0 reference desing built and working on startKIT.
Big congratulation, sounds good :)

BTW: you can still compile applications for two cores and then separate XE into two parts - one to be pre-loaded into EEPROM and second one to be feeded into binary-extraction and USB-loading process. (Some synchronization may be needed in this case.)
mhelin
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Postby mhelin » Wed Jan 15, 2014 8:34 pm

fosfor wrote:
mhelin wrote:Got the USB Audio 2.0 reference desing built and working on startKIT.
Big congratulation, sounds good :)

BTW: you can still compile applications for two cores and then separate XE into two parts - one to be pre-loaded into EEPROM and second one to be feeded into binary-extraction and USB-loading process. (Some synchronization may be needed in this case.)
That might be worth trying. However (was this already discussed) I'm wondering where the smaller binaries are used in the process of loading the images. Like with this USB audio project I get the two binaries:
image_n1c0_2.bin
image_n1c0.bin

If I use 2-tile target there will be four of them. Is it enough that the bigger ones are used, one for each tile?

Anyway, yes the tile[1] will in load faster, it should be waiting for the USB tile before starting. Would a service in the usb tile and ADC like usage (initialization) be all what is needed?
mhelin
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Postby mhelin » Wed Jan 15, 2014 9:18 pm

Ok, I'll answer myself. The smaller part code functionality can be studied using disassembler:

Code: Select all

xobjdump -d name.xe

app_usb_aud_skc_su1_2iomx.xe: file format: xcore-xe
Loadable 1 for tile[0] (node "0", tile 0):
Disassembly of section .text (size: 384)
<_start>
            0x00010000: 00 68:       ldc (ru6)       r0, 0x0
             0x00010002: 40 68:       ldc (ru6)       r1, 0x0
             0x00010004: 80 68:       ldc (ru6)       r2, 0x0
             0x00010006: c0 68:       ldc (ru6)       r3, 0x0
             0x00010008: 00 69:       ldc (ru6)       r4, 0x0
             0x0001000a: 40 69:       ldc (ru6)       r5, 0x0
             0x0001000c: 80 69:       ldc (ru6)       r6, 0x0
             0x0001000e: c0 69:       ldc (ru6)       r7, 0x0
             0x00010010: 00 6a:       ldc (ru6)       r8, 0x0
             0x00010012: 40 6a:       ldc (ru6)       r9, 0x0
             0x00010014: 00 f0 b4 d8: ldap (lu10)     r11, 0xb4 <.label0>
             0x00010018: fb 37:       set (1r)        cp, r11
             0x0001001a: 00 f0 c3 d8: ldap (lu10)     r11, 0xc3 <.label1>
             0x0001001e: eb 37:       set (1r)        dp, r11
             0x00010020: cb 6a:       ldc (ru6)       r11, 0xb
             0x00010022: bb ff ec 17: get (l2r)       r10, ps[r11]
             0x00010026: 80 f0 c0 6a: ldc (lru6)      r11, 0x2000
             0x0001002a: be 16:       add (3r)        r11, r11, r10
             0x0001002c: fb 2f:       set (1r)        sp, r11
             0x0001002e: c2 86:       getr (rus)      r0, 0x2
             0x00010030: 00 68:       ldc (ru6)       r0, 0x0
             0x00010032: 47 68:       ldc (ru6)       r1, 0x7
             0x00010034: 80 68:       ldc (ru6)       r2, 0x0
             0x00010036: 00 f0 71 d0: bl (lu10)       0x71 <write_sswitch_reg>
             0x0001003a: 02 f0 40 69: ldc (lru6)      r5, 0x80
             0x0001003e: 02 f0 88 69: ldc (lru6)      r6, 0x88

<disableLinks>:
             0x00010042: 00 68:       ldc (ru6)       r0, 0x0
             0x00010044: d4 90:       add (2rus)      r1, r5, 0x0
             0x00010046: 80 68:       ldc (ru6)       r2, 0x0
             0x00010048: 00 f0 68 d0: bl (lu10)       0x68 <write_sswitch_reg>
             0x0001004c: 15 91:       add (2rus)      r5, r5, 0x1
             0x0001004e: 06 33:       eq (3r)         r0, r5, r6
             0x00010050: 08 7c:       bf (ru6)        r0, -0x8 <disableLinks>
             0x00010052: 00 68:       ldc (ru6)       r0, 0x0
             0x00010054: 45 68:       ldc (ru6)       r1, 0x5
             0x00010056: 00 f2 82 68: ldc (lru6)      r2, 0x8002
             0x0001005a: 00 f0 64 d0: bl (lu10)       0x64 <write_sswitch_reg_no_ack>

<nodeIdLoop>:
             0x0001005e: 00 f2 42 68: ldc (lru6)      r1, 0x8002
             0x00010062: c2 86:       getr (rus)      r0, 0x2
             0x00010064: e0 17:       freer (1r)      res[r0]
             0x00010066: 81 ac:       shr (2rus)      r0, r0, 0x10
             0x00010068: 01 30:       eq (3r)         r0, r0, r1
             0x0001006a: 07 7c:       bf (ru6)        r0, -0x7 <nodeIdLoop>
             0x0001006c: 00 f2 02 68: ldc (lru6)      r0, 0x8002
             0x00010070: 65 68:       ldc (ru6)       r1, 0x25
             0x00010072: 80 68:       ldc (ru6)       r2, 0x0
             0x00010074: 00 f0 52 d0: bl (lu10)       0x52 <write_sswitch_reg>
             0x00010078: 00 f2 02 68: ldc (lru6)      r0, 0x8002
             0x0001007c: 02 f0 45 68: ldc (lru6)      r1, 0x85
             0x00010080: 00 f0 80 58: ldw (lru6)      r2, dp[0x0]
             0x00010084: 00 f0 4a d0: bl (lu10)       0x4a <write_sswitch_reg>
             0x00010088: 00 f2 02 68: ldc (lru6)      r0, 0x8002
             0x0001008c: 61 68:       ldc (ru6)       r1, 0x21
             0x0001008e: 04 f0 80 68: ldc (lru6)      r2, 0x100
             0x00010092: 00 f0 43 d0: bl (lu10)       0x43 <write_sswitch_reg>
             0x00010096: 00 f2 02 68: ldc (lru6)      r0, 0x8002
             0x0001009a: 02 f0 41 68: ldc (lru6)      r1, 0x81
             0x0001009e: 00 f0 81 58: ldw (lru6)      r2, dp[0x1]
             0x000100a2: 00 f0 3b d0: bl (lu10)       0x3b <write_sswitch_reg>

<setDimensionReg>:
             0x000100a6: 00 f2 02 68: ldc (lru6)      r0, 0x8002
             0x000100aa: 4c 68:       ldc (ru6)       r1, 0xc
             0x000100ac: 00 f0 82 58: ldw (lru6)      r2, dp[0x2]
             0x000100b0: 00 f0 34 d0: bl (lu10)       0x34 <write_sswitch_reg>
             0x000100b4: 00 f2 02 68: ldc (lru6)      r0, 0x8002
             0x000100b8: 4d 68:       ldc (ru6)       r1, 0xd
             0x000100ba: 00 f0 83 58: ldw (lru6)      r2, dp[0x3]
             0x000100be: 00 f0 2d d0: bl (lu10)       0x2d <write_sswitch_reg>

<sayHello5>:
             0x000100c2: 00 f2 02 68: ldc (lru6)      r0, 0x8002
             0x000100c6: 02 f0 45 68: ldc (lru6)      r1, 0x85
             0x000100ca: 00 f0 80 58: ldw (lru6)      r2, dp[0x0]
             0x000100ce: dd a6:       mkmsk (rus)     r3, 0x1
             0x000100d0: 58 69:       ldc (ru6)       r5, 0x18
             0x000100d2: 7d 22:       shl (3r)        r3, r3, r5
             0x000100d4: 2b 40:       or (3r)         r2, r2, r3
             0x000100d6: 00 f0 21 d0: bl (lu10)       0x21 <write_sswitch_reg>

<invokeXsscHello5>:
             0x000100da: 00 f2 03 68: ldc (lru6)      r0, 0x8003
             0x000100de: 02 f0 40 68: ldc (lru6)      r1, 0x80
             0x000100e2: 00 f0 84 58: ldw (lru6)      r2, dp[0x4]
             0x000100e6: dd a6:       mkmsk (rus)     r3, 0x1
             0x000100e8: 58 69:       ldc (ru6)       r5, 0x18
             0x000100ea: 7d 22:       shl (3r)        r3, r3, r5
             0x000100ec: 2b 40:       or (3r)         r2, r2, r3
             0x000100ee: 00 f0 15 d0: bl (lu10)       0x15 <write_sswitch_reg>

<setXsscSysFreq5>:
             0x000100f2: 00 f2 03 68: ldc (lru6)      r0, 0x8003
             0x000100f6: 01 f0 51 68: ldc (lru6)      r1, 0x51
             0x000100fa: 80 68:       ldc (ru6)       r2, 0x0
             0x000100fc: 00 f0 0e d0: bl (lu10)       0xe <write_sswitch_reg>

<sayHello1>:
             0x00010100: 00 f2 02 68: ldc (lru6)      r0, 0x8002
             0x00010104: 02 f0 41 68: ldc (lru6)      r1, 0x81
             0x00010108: 00 f0 81 58: ldw (lru6)      r2, dp[0x1]
             0x0001010c: dd a6:       mkmsk (rus)     r3, 0x1
             0x0001010e: 58 69:       ldc (ru6)       r5, 0x18
             0x00010110: 7d 22:       shl (3r)        r3, r3, r5
             0x00010112: 2b 40:       or (3r)         r2, r2, r3
             0x00010114: 00 f0 02 d0: bl (lu10)       0x2 <write_sswitch_reg>
             0x00010118: 00 f0 3e d0: bl (lu10)       0x3e <.label2>

<write_sswitch_reg>:
             0x0001011c: 0c f3 cc 68: ldc (lru6)      r3, 0xc30c
             0x00010120: c1 6a:       ldc (ru6)       r11, 0x1
             0x00010122: 00 f0 05 73: bu (lu6)        0x5 <write_switch_reg>

<write_sswitch_reg_no_ack>:
             0x00010126: 0c f3 cc 68: ldc (lru6)      r3, 0xc30c
             0x0001012a: c0 6a:       ldc (ru6)       r11, 0x0
             0x0001012c: 00 f0 00 73: bu (lu6)        0x0 <write_switch_reg>

<write_switch_reg>:
             0x00010130: 00 55:       stw (ru6)       r4, sp[0x0]
             0x00010132: c1 ac:       shr (2rus)      r4, r0, 0x10
             0x00010134: 1e 71:       bt (ru6)        r4, 0x1e <write_switch_reg_return_0>
             0x00010136: c5 ac:       shr (2rus)      r4, r1, 0x10
             0x00010138: 1c 71:       bt (ru6)        r4, 0x1c <write_switch_reg_return_0>
             0x0001013a: 81 a4:       shl (2rus)      r0, r0, 0x10
             0x0001013c: 03 40:       or (3r)         r0, r0, r3
             0x0001013e: 02 87:       getr (rus)      r4, 0x2
             0x00010140: 90 17:       setd (r2r)      res[r4], r0
             0x00010142: 03 f0 c0 68: ldc (lru6)      r3, 0xc0
             0x00010146: 03 4f:       outct (2r)      res[r4], r3
             0x00010148: c3 7a:       bf (ru6)        r11, 0x3 <build_return_no_ack>
             0x0001014a: 40 ad:       shr (2rus)      r0, r4, 0x8
             0x0001014c: 80 a4:       shl (2rus)      r0, r0, 0x8
             0x0001014e: 04 73:       bu (u6)         0x4 <write_switch_reg_send>

<build_return_no_ack>:
             0x00010150: 80 ac:       shr (2rus)      r0, r0, 0x8
             0x00010152: 3c a7:       mkmsk (rus)     r3, 0x8
             0x00010154: 03 40:       or (3r)         r0, r0, r3
             0x00010156: 80 a4:       shl (2rus)      r0, r0, 0x8

<write_switch_reg_send>:
             0x00010158: b4 ac:       shr (2rus)      r3, r1, 0x8
             0x0001015a: 03 40:       or (3r)         r0, r0, r3
             0x0001015c: 80 af:       out (r2r)       res[r4], r0
             0x0001015e: 94 0f:       outt (r2r)      res[r4], r1
             0x00010160: 88 af:       out (r2r)       res[r4], r2
             0x00010162: 11 4f:       outct (rus)     res[r4], 0x1
             0x00010164: c9 7a:       bf (ru6)        r11, 0x9 <write_switch_reg_free_and_return_1>
             0x00010166: 90 87:       inct (2r)       r0, res[r4]
             0x00010168: 03 b0:       eq (2rus)       r0, r0, 0x3
             0x0001016a: 11 cf:       chkct (rus)     res[r4], 0x1
             0x0001016c: e4 17:       freer (1r)      res[r4]
             0x0001016e: 00 5d:       ldw (ru6)       r4, sp[0x0]
             0x00010170: c0 77:       retsp (u6)      0x0

<write_switch_reg_return_0>:
             0x00010172: 00 68:       ldc (ru6)       r0, 0x0
             0x00010174: 00 5d:       ldw (ru6)       r4, sp[0x0]
             0x00010176: c0 77:       retsp (u6)      0x0

<write_switch_reg_free_and_return_1>:
             0x00010178: e4 17:       freer (1r)      res[r4]
             0x0001017a: 01 68:       ldc (ru6)       r0, 0x1
             0x0001017c: 00 5d:       ldw (ru6)       r4, sp[0x0]
             0x0001017e: c0 77:       retsp (u6)      0x0
:

It seems that the code sets up the switch and opens some channels (says hello so to say) so you might have to that yourself in XC code.

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