Cam Xcore read pixels at 26.6 MHz 10 bits parallel

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uth
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Cam Xcore read pixels at 26.6 MHz 10 bits parallel

Postby uth » Wed Jan 23, 2019 8:57 am

Hello, there is a camera chip MT9V022 which outputs pixels at 26.6 MHz, single pixel data is 10 bit parallel. Start of a line readout can be triggered externally. Would bigbanging with Xcore 200 be fast enough to support chips like that?
uth
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Postby uth » Wed Jan 23, 2019 10:59 am

The clock of the chip can be set within the range 13.0 to 27.0 MHz. Is it possible that Xcore produces a master clock 100.0*8/30 = 26.66 MHz for the chip? It would allow an asynchronous reading of the pixels, as clock out is simply the master clock inverted.
The question is, can xcore integrate 10, or at least 8, input pins into a word and store it within a sufficient time?
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mon2
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Postby mon2 » Wed Jan 23, 2019 4:40 pm

Hi. Yes, it is possible.

Recommended reading:

1) Review the code sample at the following URL with title "The following program configures a port to synchronise the sampling of data to an external clock."

https://www.xmos.com/developer/publishe ... and-output

2) Suggest that you allocate a SINGLE BIT port to accept an external clock source.

3) Then drive the above SINGLE BIT port with an external PLL such as the very low cost Si5351 which operates from a 25 Mhz crystal (not an oscillator) and is < $ 1 USD. Adafruit has a low cost test board < $ 9 USD from Arrow (free shipping) that will serve your project well for testing. Using I2C routines with the XMOS CPU, program this PLL (using the Silabs Clock Builder tool - free) and prime the registers to clock out your desired clock with precision. Also drive the same clock to your camera module - you may want to buffer the clocks to each, the XMOS input and again for the camera module - keeping the same skew.

Then proceed to apply as per the above brief article. There are many other documents on the same topic but be sure to allocate the proper ports for the 8 bit access. Chime back if you need other pointers.
uth
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Postby uth » Fri Jan 25, 2019 1:17 pm

Thanks mon2. But why not make xcore generate the 25MHz clock for the camera chip? Because it would waste processor resources for a simple task?
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mon2
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Postby mon2 » Fri Jan 25, 2019 1:29 pm

You can consider to do this but the granularity of the clock generation is much more flexible using a true PLL such as the SI5351A. Also, can serve as the XMOS CPU clock. XMOS built a factory OTP programmed component from Silabs where there are 3 pre-defined clock outputs upon power up. This is a nice to have for most project. Bear in mind that internally there are 2 independent clock generators so be sure to assign a dedicated one for say your CPU input clock and use the other for the camera clock. This way, you do not disturb the CPU clock (ie. CPU would be clock-less) during any changes to the other clock. You will always want a glitch free method of clock changes. Otherwise you can lock up the CPU. This is only an idea to use the Si5351A for "any desired" clock value on the fly.

Alternatively, use a fixed clock oscillator for the CPU and use this clock and divide by 4 and output to a single bit port. That is 100MHZ/4 = 25 Mhz for your camera clock. Best to test your idea before applying to a custom PCB layout.

Reference:
https://www.xmos.com/developer/publishe ... and-output

For more details than you may care for on the PLL :), please review this thread:

viewtopic.php?t=4599

and full source code to program the Si5351A (even the OTP version) over I2C on XMOS CPU:

viewtopic.php?t=4647&start=10

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