The XUF216 device has two tiles - each with a 500MHz processor which can support dual issue (2 instructions per clock). Each tile has up to 8 logical cores which share this processing. So peak throughput is 500 * 2 * 2 = 2000MIPS for the XUF216 chip. These are "will not exceed" numbers. More useful info is that a well written FIR (like those used in PDM decimators) can achieve around 2 cycles per tap.
If you connect 32 MEMS PDM microphones to a XUF216, you will have just enough MIPS to get samples on to TDM and about 62.5 MIPS for DSP. However you could use an XUF232 and you would have two whole tiles free.
The PDM clocks are synchronised. Each of the channels are precisely synchronised right through the decimation filters to PCM. This is needed for DoA, beamforming and other algorithms that require subsample precision.
If you have a simple question and just want an answer.
1 post • Page 1 of 1
- Experienced Member
- Posts: 69
- Joined: Thu Dec 10, 2009 7:08 pm
Who is online
Users browsing this forum: No registered users and 3 guests