Built in interpreters, VMs and runtime shells

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shawn
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Re: Built in interpreters, VMs and runtime shells

Postby shawn » Fri Feb 05, 2010 1:27 am

Java VMtm is a product for sparc and will be bound SUN.
I like SUN, pretty good company. Still that limits control.

There's a lot of dimm bound, naturally, vm's.
The best VM for xcore is... I don't know.

I really like the OTP idea .
8K seems small.
Then again the TX-0 instructions were 2bits.
In an 18bit machine that leaves 16bits for addressing.
Thats it at the low layer, of course it was built up from there.
I kinda think of it as a road map, cause I think we should map
a VM explictly for Xcore with extentions to VM per core OTP @ 8K.

I was contemplating something more a long the lines of cellular automata VM
say using 1d machines like rule110 for construct linked via XC or and C++.
Because the Xcore can CSP the more cores the more flexibility for the VM.
Especially considering OTP giving US a means to extensible, on chip IP licensing.

On the other hand the Tranputer is kin to Xcore It would be a good plan also.
I'm fairly sure someone will link Tvm's to Xcore its just I think the time would be best
bet on creating, somethng never done before to take best advantage of Xcores potential.

Funtion must fit form. a good VM would realize form to funtion therfore being very mallable.
If that makes any sense...

Shawn
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Postby Heater » Fri Feb 05, 2010 11:49 am

How about a ZPU virtual machine running C code compiled with GCC from external RAM?

As I said before, what I'd like to see is a way to execute code from an external RAM. Even if it is only 64, 128, 256, 512K bytes of static RAM. That's easy enough to add to an XMOS. In the extreme, where speed is not important even an attached SPI RAM would do. Could still be useful for reams of user interface code or such like.

As the XMOS cannot directly map external RAM into it's address space and execute code from there it would require a virtual machine running on the XMOS to execute byte codes on from the external RAM.

Just now I'm looking at the ZPU core. This is designed to be the "smallest 32 bit CPU in the world" for use in FPGA's. It has a minimal instruction set, is stack based, and all op codes are 8 bits wide. The brilliant part about the ZPU is that there is a version GCC targeted at its instruction set.

The ZPU could be implemented as an interpreter/VM on an xcore easily. Even in the OTP.

http://opensource.zylin.com/zpudocs.html
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TonyD
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Postby TonyD » Sun Feb 07, 2010 8:01 pm

The ZPU seams a very interesting minimalist 32-bit architecture. 8-bit wide opcodes.,11 instructions - it doesn't get much minimalist than that :)

I'm like the idea of a XS1 VM and ZPU's byte wide op code would definitely lend itself to using a simple external SRAM for both program and data memory storage. You could boot ZPU code from a SD card straight into the SRAM and interpret code from there. The 8K OTP might be enough for both a SD card boot loader and ZPU interpreter.
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Postby Heater » Sun Feb 07, 2010 10:38 pm

I have just created a ZPU virtual machine in C working from the source code of ZyLins ZPU simulator which is Java. It comes it at 8.5Kbytes as a Linux executable. I'll try at get it compiled for XMOS when I have a moment and see if we can get it down to OTP size.
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Postby TonyD » Mon Feb 08, 2010 9:49 am

That's great. Can you post the code?
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Postby Heater » Mon Feb 08, 2010 10:36 am

Sure TonyD. Let me get it into a usable state and give it a little bit of testing first.

Just now it's not clear to me how to get the ZPU GCC tool chain to give me a binary for loading into the ZPU RAM space.
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jonathan
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Postby jonathan » Mon Feb 08, 2010 5:06 pm

I wrote a really useful interpreter. It emulates an extremely lean processor. The processor definition can be found here:

http://www.cs.bgu.ac.il/~yoavg/quines/sic.html

The code - in an extremely ugly first draft - is below.

Code: Select all

#include <stdio.h>

#define MEM_SIZE 1000
#define INSTR_SIZE 300
#define DATA_START 2
#define PROG_END -100
#define DATA_END -200
#define EXE_PROG -300
#define MEM_REQ_END -400

int memory[MEM_SIZE];
int instructions[INSTR_SIZE];

void feeder(chanend a);
void sic(chanend a);

int main() {

 chan a;

 memory[0]=0; // Initialize location 0 with constant 0
 memory[1]=1; // Initialize location 1 with constant 1

 par {
  feeder(a);
  sic(a);
 }

}

void sic(chanend a) {
 // Receive a program over channel
 // Copy instructions into instruction memory

 // Place any initial memory values (program variables)

 int i=0;
 int end=0;

 int temp_var=0;

 int instr=0;
 while (temp_var!=PROG_END) {
  a :> temp_var;
  if (temp_var!=PROG_END) instructions[instr] = temp_var;
  instr++;
 }

 instr=DATA_START;
 while (temp_var!=DATA_END) {
  a :> temp_var;
  if (temp_var!=DATA_END) memory[instr]=temp_var;
  instr++;
 }

 while (temp_var!=EXE_PROG) {
  a :> temp_var;
 }

 while (end==0) {
  memory[instructions[i]]=memory[instructions[i]]-memory[instructions[i+1]];
  if (memory[instructions[i]]<0) {
   i=instructions[i+2];
  } else {
   i = i+3;
  }
  if ((instructions[i]==0)&(instructions[i+1]==0)&(instructions[i+2]==0)) {
   end=1;
  }
 }

 while (temp_var!=MEM_REQ_END) {
  a :> temp_var;
  if (temp_var!=MEM_REQ_END) a <: memory[temp_var];
 }

}

void feeder(chanend feeder_channel) {

 // This program multiplies a by b and receives back the result
 int a=10;
 int b=3;
 int c_result;

 //start: sbn temp, temp, .+1    # Sets temp to zero
 feeder_channel <: 5;
 feeder_channel <: 5;
 feeder_channel <: 0;

 //loop:  sbn b, one, done       # Decrease b by one, branch if it was zero
 feeder_channel <: 2;
 feeder_channel <: 1;
 feeder_channel <: 9;

 //sbn temp, a, loop      # Subtract a from temp and loop back
 feeder_channel <: 5;
 feeder_channel <: 3;
 feeder_channel <: 3;
 
 //done:  sbn c, c, .+1          # Set c to zero
 feeder_channel <: 4;
 feeder_channel <: 4;
 feeder_channel <: 0;

 //sbn c, temp, .+1       # Set C to product
 feeder_channel <: 4;
 feeder_channel <: 5;
 feeder_channel <: 0;

 feeder_channel <: PROG_END;

 feeder_channel <: a;
 feeder_channel <: b;
 feeder_channel <: DATA_END;

 feeder_channel <: EXE_PROG;

 // Request particular memory locations
 feeder_channel <: 4;
 feeder_channel :> c_result;
 feeder_channel <: MEM_REQ_END;

 printf("%i\n", c_result);

}
:shock:




:lol: :lol:
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leon_heller
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Postby leon_heller » Mon Feb 08, 2010 5:22 pm

Is it "Turing Complete"? :D

Leon
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jonathan
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Postby jonathan » Mon Feb 08, 2010 5:29 pm

leon_heller wrote:Is it "Turing Complete"? :D

Leon
Left as an exercise for the reader.
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shawn
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Postby shawn » Tue Feb 09, 2010 8:14 am

yourfirstdraftcodeisnotmessyCby$$.$$herVirosnaturecan0nly$peek$Blaspheme::)

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