Several questions about XMOS

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Sink0
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Several questions about XMOS

Postby Sink0 » Thu Sep 30, 2010 2:38 pm

Hi, i got some questions about XMOS technology.

I was looking at the datasheet and as i understood it is possible to run hard mult-thread at a XMOS. Is this real hard or just a real fast processor that process all the threds in on a big line (as a common processor). The 400 MIPS of perfomance is just achivable using all the threads or can i achive it with just one thread? How reliable is the technology? Can i use it on high end applications?

Thank you!
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leon_heller
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Postby leon_heller » Thu Sep 30, 2010 3:08 pm

Threads are implemented in hardware and are processed in round-robin style, switching in one clock. Each thread can run at 100 or 50 MIPS, so you can have eight 50 MIPS threads or four 100 MIPS threads, or a mixture of 100 and 50 MIPS threads, as long as the total doesn't exceed 400 MIPS.
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Bianco
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Postby Bianco » Thu Sep 30, 2010 3:23 pm

leon_heller wrote:Threads are implemented in hardware and are processed in round-robin style, switching in one clock. Each thread can run at 100 or 50 MIPS, so you can have eight 50 MIPS threads or four 100 MIPS threads, or a mixture of 100 and 50 MIPS threads, as long as the total doesn't exceed 400 MIPS.
That's not entirely true.

With n threads:

n <= 4 each thread will get a guaranteed (total MIPS / 4) MIPS which is also the maximum.
With n > 4 each thread get a guaranteed (total MIPS / n) MIPS with a maximum of (total MIPS / 4) MIPS depending on the CPU usage of other threads.

So if you run only one thread, you can only utilize 1/4th of the available processing power.

The CPU design is very much a Barrel Processor.
How reliable is the technology? Can i use it on high end applications?
So far there have not been any major problems, so it can be considered reliable. What kind of high end applications are we talking about?
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Postby Sink0 » Thu Sep 30, 2010 3:36 pm

But as i looked at the datasheet there is no available hardware peripheral. Is that correct? I am supposed to emulated these with a thread?

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leon_heller
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Postby leon_heller » Thu Sep 30, 2010 3:52 pm

Many peripherals are implemented in software. For others, such as ADCs, an external chip is required.
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Postby Sink0 » Thu Sep 30, 2010 4:46 pm

What would be the minimum hardware so i can create a breakout board? (with no voltage regulation on it)

Thank you
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Folknology
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Postby Folknology » Thu Sep 30, 2010 5:00 pm

Assuming an L1, without voltage regulation, you need to provide both 1volt (for the core) and 3.3volt for the I/O. The power up must be sequenced (and should be monitored, see design checklist). You will also probably need to add flash for program storage (as none is included) and something to program it with like an xtag (Xmos Jtag), so allow for a 2*10 pin header. You will also need a crystal oscillator, decoupling caps, and a series rc low pass for the PLL supply

Xmos L1-64 example reference design

Regards
Al
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Postby vanjast » Mon Nov 01, 2010 12:50 am

Bianco wrote:
leon_heller wrote:Threads are implemented in hardware and are processed in r
n <= 4 each thread will get a guaranteed (total MIPS / 4) MIPS which is also the maximum.
Are you sure about this, wrt a single thread (and round robbin distibution).
Your calc doesn't make sense, unless Xmos are not telling us something ??
:shock:
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lilltroll
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Postby lilltroll » Mon Nov 01, 2010 12:12 pm

With at least 4 threads and a four stage pipeline, you get a "smart" solution.
I believe it works like this:

Instruction Execution

Each thread has a short instruction buffer (64-bits) sufficient to hold at
least four instructions. (dependent on the size of the instruction)

Instructions are issued from the instruction buffers of the
runnable threads in a round-robin manner.

Threads which are not in the run set are ignored.
Instruction fetch is performed within the execution pipeline, in
the same way as data access.


Execution pipeline


Simple four stage pipeline:

Code: Select all

1 decode              reg-write
2                     reg-read
3 address             ALU1 resource-test
4 read/write/fetch    ALU2 resource-access schedule
At most one instruction per thread in the pipeline.

http://www.cs.bris.ac.uk/~dave/ietcamb.pdf
Probably not the most confused programmer anymore on the XCORE forum.
omega7
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Postby omega7 » Thu Apr 07, 2011 8:47 am

An interesting thread guys! I read the document from David May and gives a nice overview about the XMOS techniques and theory.

But not really clear to me yet about the round robin thread scheduler:

Does it execute a single clock cycle on each thread before continuing to the next thread, or is it instruction based or is it buffer based containing a set of instructions?

martin

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