Hi,
I'd like to be able to connect the XCORE.AI multichannel kit to some external HW and use the kit to stream the TDM channels from external HW (instead of the onboard ADCs) to USB. As I understand, for this I need to configure the XCORE.AI to be TDM Slave (one of the configurations in 7.3.1 supports this) and also route the physical pins instead of the on-board DACs to a connector that i can use with external HW (which is TDM Master). From this post https://www.xcore.com/viewtopic.php?t=8379 and user manual I see that I potentially can use J38 and need to remap the BCLK, LRCLK and I2S_ADC0 to the pins of J38. Do I need to make the changes only in the xk-audio-316-mc.xn only or is there any other files I need to update? Like general GPIO settings? Also, do these pins on J38 (X1D49-X1D58) support I2S/TDM connection?
Thanks!
XK-AUDIO-316-MC - how to remap I2S/TDM pins for external connection (J38?) Topic is solved
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Alex-SRL
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fabriceo
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Hi Alex and welcome
First of all, the MC board has plenty of possibilities but there is one limitation : the master clock (22 or 24.576mhz) must be provided by the MC board itself (PLL based). I cannot see on the schematic v1.1 a solution to inject your own master clock (which is mandatory) on the MCLK_XMOS wire.
Then yes the TDM flow can be master from your ADC and come into the MC board, but you cannot use J38 as none of the pins are connecte to so called "1bit" ports.
you should use a dedicated lrclk and bclk inputs on the xmos instead of using the existing one to avoid any electrical conflict.
Here I suggest J1.7 and J1.9 which are available and compatible with 1 bit port buffering.
finaly your ADC data line could be connected to X_ADC_D0 on J7, by removing the existing J6 jumper to avoid conflict with on board ADC.
then for the software, yes you could change this in the board .xn file, but I would instead configure these new pins inside the xua configuration file.
best of luck
First of all, the MC board has plenty of possibilities but there is one limitation : the master clock (22 or 24.576mhz) must be provided by the MC board itself (PLL based). I cannot see on the schematic v1.1 a solution to inject your own master clock (which is mandatory) on the MCLK_XMOS wire.
Then yes the TDM flow can be master from your ADC and come into the MC board, but you cannot use J38 as none of the pins are connecte to so called "1bit" ports.
you should use a dedicated lrclk and bclk inputs on the xmos instead of using the existing one to avoid any electrical conflict.
Here I suggest J1.7 and J1.9 which are available and compatible with 1 bit port buffering.
finaly your ADC data line could be connected to X_ADC_D0 on J7, by removing the existing J6 jumper to avoid conflict with on board ADC.
then for the software, yes you could change this in the board .xn file, but I would instead configure these new pins inside the xua configuration file.
best of luck
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Joe
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I would try to stick to the TDM slave config in the USB audio firmware as much as possible. That should work as is, using the same pins which you can wire into on J7. The only change that you would need to make is to configure the jumpers correctly (to disconnect TDM data lines from DACs/ADCs) and also you would also need to change the part of the code that configures the DACs for TDM mode as that configures one of the DACs to output LRCK/BCLK and these would contend with the LRCK/BCLK that you would be feeding in externally.
As Fabriceo says, default is that the MC audio board is clock (MCLK) master so it would output MCLK (on J7) to your clock slave from which you would output BCLK and LRCK (and TDM data) back to the MC audio board. Other clock configs are possible but a little more tricky to wire in as no dedicated header.
Cheers,
Joe
As Fabriceo says, default is that the MC audio board is clock (MCLK) master so it would output MCLK (on J7) to your clock slave from which you would output BCLK and LRCK (and TDM data) back to the MC audio board. Other clock configs are possible but a little more tricky to wire in as no dedicated header.
Cheers,
Joe
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Alex-SRL
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Hi fabriceo and Joe,
thank you for your answers.
Understood now, the main limitation is the MC has to be the one generating MCLK and then I should use the MCLK to generate BCLK and LRCLK (i was not aware of that).
I'll use J7 then as Joe suggested and change the onboard ADC configuration to not generate the LRCLK and BCLK (or probably put the onboard ADC in reset?).
Thanks again!
Alex
thank you for your answers.
Understood now, the main limitation is the MC has to be the one generating MCLK and then I should use the MCLK to generate BCLK and LRCLK (i was not aware of that).
I'll use J7 then as Joe suggested and change the onboard ADC configuration to not generate the LRCLK and BCLK (or probably put the onboard ADC in reset?).
Thanks again!
Alex