AEC mode and channels on the same slice.

Technical discussions around xCORE processors (e.g. xcore-200 & xcore.ai).
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Bob
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Joined: Thu Oct 28, 2010 3:51 pm

AEC mode and channels on the same slice.

Post by Bob »

Hi All,
Been working through the aec power saving modes using an XC-1A devboard. Quad slice package stays nice and kool, however I found a caveat in the aec documentation that is somewhat troubling:
'The xCORE Tile will not enter standby when logical cores are paused waiting for channel communication across a single xCORE Tile.'

Now this seems to imply that if I code a multirate control system on a single slice and use channels for interprocess coms, then the chip will never idle.. it would though be usual to have both port and timer inputs to the same process also, so the process has no reason to stay in impatient hypermode.
Have I made some conceptual error here? ..perhaps there is something in relation to sequential processing or maybe some way of prioritising or guarding the internal channel inputs.
I need to develop systems that can switch to battery mode, so transient/latent power control is essential. This is the reasoning behind my questioning.

..and a second question, in Occam we had pri par and pri alt. Can these be replicated in xc? I used these a lot in realtime systems.

..and a third question :/ The XC-1A board has a jtag interface thus I presume not jtag2. I've found the debugger to be fractious and unstable if singlestepped. Would this be the reason?


richard
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Joined: Tue Dec 15, 2009 12:46 am

Post by richard »

Bob wrote:Hi All,
Been working through the aec power saving modes using an XC-1A devboard. Quad slice package stays nice and kool, however I found a caveat in the aec documentation that is somewhat troubling:
'The xCORE Tile will not enter standby when logical cores are paused waiting for channel communication across a single xCORE Tile.'
I've checked with our silicon team and the tile should go into standby mode when all the logical cores on that tile are paused waiting for resources. It shouldn't matter whether the resource it is paused on is a channel end connected to another tile or a channel end connected to the same tile. The document has been updated.
..and a second question, in Occam we had pri par and pri alt. Can these be replicated in xc? I used these a lot in realtime systems.
You can use #pragma ordered to change the priority of cases in a select, see:

http://www.xmos.com/en/support/document ... ed_example
..and a third question :/ The XC-1A board has a jtag interface thus I presume not jtag2. I've found the debugger to be fractious and unstable if singlestepped. Would this be the reason?
You are correct that the debug adapter for the XC-1A is different to the xtag2 debug adapter. Debugging won't be as fast as it would be with an xtag2, but it should be fully functional. What issues do you see?
Bob
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Joined: Thu Oct 28, 2010 3:51 pm

Post by Bob »

Hi Richard,
This is all very helpful. Thank you.
I had already seen evidence that the slice would go into standby whilst waiting for intercommunication, as the timers slowed as per core clock, so was having trouble interpreting the meaning of the misleading statement above.
Can I pause in the debugger and inspect pr 2 to deduce the current state? ..or are these values just a general setting for aec mode? Are there other mechanisms that can be used to detect the state of Standby Mode?

That #pragma will certainly be put to good use. Thanks for the info.

I have an XK-1A board also which has not yet been used, so will use this for the more challenging debugging. The intention was to develop a delta-sigma A/D converter, thus the XC-1A prototyping area was best suited.
I was finding that the XC-1A sometimes does not return using the stepover button. Sync is lost completely and even pause seems not to then work. It is used with a high spec quad core desktop machine with vista at present. Later I'll return to suse linux when the project work starts for real. I've noted that stepping over any timeafter statement usually ends in loss of synch but it happens in other places too less frequently. When a pattern becomes apparent then I'll add clearer description.

Also on a differing subject, have a difficulty with accessing this forum and need to request a onetime login every time. I've tried a selection of passwords which are accepted as high security, save the settings but have never been able to use them to log in. I'm sure I'm not the only one encountering this issue.
Bob
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Posts: 11
Joined: Thu Oct 28, 2010 3:51 pm

Post by Bob »

Hi Richard,
Been experimenting with the XK-1A and as you say, the jtag2 interface is extremely responsive and usable. I've managed to loose control of the processor a couple of times but by clicking on pause/resume randomly it appears to come back or finds a breakpoint somewhere. This is already looking to be far more stable than most ice kit I've used in the past.
I also wonder if the 'loss of control' is because of timer behaviour, which leads to yet another question. Are the timers halted when in breakpoint or suspend mode? I'd assumed not and this could account for the long delays if the timer has wrapped. (It also looks like something of a nightmare to achieve across multi slices/chips because there is no guarantee that the clocks are synched..).
I'll learn to drive the debugger with the XK and then go back to the jtag1/G4 combo.
Is there a hotkey I can use to singlestep through the dissassembly?

Another potential issue I've inadvertently introed in relation to the G4 is by using the same function across tiles, so a breakpoint is not a unique venue.. :/ Perhaps abstraction does not always works to your favour, then.. hmmmph.

Is the source for the demo preloaded on the XC-1A available for interested folk? There is clearly a lot of detail timing going on across tiles to achieve those cycling multicolour patterns. I'd like to read through the project to see how it is structured.
I would like to use xcore to control banks of high speed, high performance hydraulic valves. There is a similarity here because there is a need to combine complex frequency related dither patterns with the output current drive for position/flow control or the spool valve sticks.

Some mastery over xscope is the next conquest now jtag2 is running.
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