RST_N, MODEx possible race condition?

Technical discussions around xCORE processors (e.g. General Purpose (L/G), xCORE-USB, xCORE-Analog, xCORE-XA).
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jdfenley
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RST_N, MODEx possible race condition?

Post by jdfenley »

When exactly are the MODEx pins sampled? If I read the datasheets correctly, they are sampled when RST_N is de-asserted (goes high). Connecting MODE2 and MODE3 to TRST_N from the JTAG header allows the device to boot from JTAG when XTAG is plugged in, and boot from SPI (Flash) when the XTAG is not plugged it.

But many of the schematics for the XMOS reference designs show that the power supervisory circuit also drives TRST_N (along with RST_N) through an open-drain buffer. Thus, when the power supervisory circuit de-asserts RST_N, the signals TRST_N, MODE2 and MODE3 pins transition from 0 to 1 at the same time. Doesn't this create a race condition between RST_N and MODE2 and MODE3 pins?

I've attached a snippet of the USB Audio 2.0 Ref Design schematic regarding this.

Thanks in advance,
John
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segher
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Post by segher »

Yes, this looks fishy.

Most new designs connect TRST and RST together (on the chip) and use TRST on the XSYS connector only to drive the MODE pins (this signal was renamed to MSEL btw). This is much simpler and works just fine (you lose the ability to reset JTAG asynchronously, but that is never needed on L-series chips).
bearcat
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Post by bearcat »

Hmmm... Why hadn't I thought of doing that. Sounds much cleaner, will modify. The XTAG2 appears to hold TRST for another 400uS after reset. No race condition there.

One additional question I have also had on this same line is pullups. The docs seem a little vague to me. Not trying to hijack this thread.

Can the mode, rst, jtag lines, and trst float (not connected), and be assured high? I.E. no pullups and no active drive, open collector for example. Not talking about actually reseting the device, here, just the inputs.

Also, is there any advantage with holding the JTAG interface in reset for production devices?
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segher
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Post by segher »

bearcat wrote:Can the mode, rst, jtag lines, and trst float (not connected), and be assured high? I.E. no pullups and no active drive, open collector for example.
The device has internal pullups, but those are not strong enough to reliably pull up anything external. If what they would be pulling up is just a piece of dead metal on your board I wouldn't worry; but if it goes to a connector (like XSYS) with who-knows-what connected to it...

Resistors are cheap.
Also, is there any advantage with holding the JTAG interface in reset for production devices?
You have to reset the TAP at bootup; just tying TRST to ground is the cheapest way to do that (if you are absolutely sure you will not need to debug the production devices!)
mmar
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Post by mmar »

Seems i have issue with this together connected MODE23 and TRSTN from open drain logic.
I use this on XS1-L8A-128 and my design not start on first power on.
Seems wait for start from JTAG. (nothing connected to XTAG)
Second start is ok from SPI. (power off - on)

I test it on 10 pcs and now 30%-40% have this issue. Other pcs start ok firstly.

How solution is for this random boot definition protect?
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segher
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Post by segher »

Could you show the relevant part of your schematic please?
It's rather hard to guess without it :-)
mmar
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Post by mmar »

Schematics attached
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segher
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Post by segher »

Yes, this looks exactly like the problem in the original post
here.

If the reason some of your boards don't boot is indeed that
MODE2,3 are sampled low (you didn't say if (and how) you
checked, or if it is just an assumption), it might work better
if you add a (strongish) pull-up resistor on it (so on the open
drain buffer output). This is a good plan anyway, don't rely
on the internal pullups. But better of course is not to pull the
MODE2,3 pins low on a regular reset at all :-)
mmar
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Post by mmar »

I try 3k9 pull up this mix signal and seems help start ok. I make more tests and write result.
Leif
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Post by Leif »

I have designed three circuit boards that have XMOS XS1-L8A-TQ128. All have had startup problems, some due to simple reasons. Latest board had our first ever Spartan6 FPGA on the same board and it worked and programmed fine from the first boot-up.

I have tried to use XK-1A as an example but something goes wrong. I just recently found reference design with NCP303LSN09 for RST_N booting, but it is not 100% clear how to drive the RST_N, TRST_N, MODE2 and MODE3 and what pull-up resistor one should have and where.

So if there exist a known working reference design that uses header for XTAG2 programming/debugging and drives correctly MODE2, MODE3, TRST_N and RST_N I think it would be valuable for designers.

br,

\leif