Clock and Reset timing

Technical discussions around xCORE processors (e.g. General Purpose (L/G), xCORE-USB, xCORE-Analog, xCORE-XA).
User avatar
Posts: 9
Joined: Wed Nov 02, 2011 2:49 am

Clock and Reset timing

Post by yamada »

Hi, all

I maked custom board unsing XS1-G4.
It's almost the same as XC-1A.

Dozens are maked and all of them are work fine, but I found a suspicious point on boot sequence.
SS_RESET is taken high before clock is supplied to CPU.

The order of these signals are written in Datasheet...

> The PLL is used to generate all on-chip clocks. SS_CLK is the reference clock input.
> It should be supplied with a clock with monotonic rising edges and should be
> stable before SS_RESET is taken high.

My boards are work, still not keeping above timing.
Will my boards have a trouble in the future?

Posts: 12
Joined: Mon Oct 26, 2015 11:06 am

Post by will1979 »

Yes, generally chips need a clock before they are taken out of reset; without it, odd things may happen, including them not working randomly.