opinions regarding proposed implementation etherernet+sdram

Technical discussions around xCORE processors (e.g. General Purpose (L/G), xCORE-USB, xCORE-Analog, xCORE-XA).
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boeserbaer
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opinions regarding proposed implementation etherernet+sdram

Postby boeserbaer » Wed Apr 21, 2010 3:14 am

I am trying to get the following implemented:

core 0 L1-128 with lan8700 for ethernet connection
5bit link
core zero link D to core 1 link C
core 1 L1-128 with sdram for huge FIFO

Boot scenario(s):

over jtag during development (xtag-2)
core 0 over spi boots core 1 over xlink
note second 2bit xlink for booting:
core 0 link A to core 1 link B

Some questions:
1. is booting core 1 via its link B probably workable?
2. Is the movement of the CS WE RAS and CAS from a 4 bit port to 4 1 bit ports likely to cause issue? It would be needed to free up port B for boot over xlink
3. Any issues mixing 2 bit and 5 bit links between 2 cores?
4. Are all 1 bit ports equal. I moved some bits from the XC-2 reference design to allow normal SPI boot, and am worried about clocks and buffered ports.
Any obvious errors (besides missing power and config?

Thanks in advance for any help. I will report on my results (making a simple server (not http just TCP) and attempting to move real-time data from xmos to a pc (QT application). I am hoping to get over 4Mbyte / s with around 1k packets. Data to be pushed from external 2bit link through core 1 where it is stored in memory. Data is pulled by core 0 from core 1 memory as fast as the ethernet will take it. Plan on using burst mode moving about 1k at a time.

Regards,
mike


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Woody
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Postby Woody » Wed Apr 21, 2010 8:50 am

1. Yes booking core 1 via link B is definitely doable.

2. Yes moving to 4x1bit ports from 1x4bit port is fine.

3. No and yes: you can mix 2 and 5 wire links between cores but you need to configure it correctly. Firstly, do you really need to have the 2 wire link? You can successfully boot down the 5 wire link in 2 wire mode. The 5 wire link will be faster, and unless you need to have a streaming channel or have two packets being transferred simultaneously, having a single 5 wire link can give you better performance. Why? When a packet is routed, it may take either the 2wire or 5wire link. This means that some packets will be transferred quickly, but on the next iteration of the same code, the transfer may be slower down the 2 wire link. To get around this you could setup two separate 'networks' and assign the two links to separate networks, you need to ensure that any channelEnd you're sending data down is configured to use the network you want it to.

4. Not all 1 bit ports are identical, but they are very similar and you'll usually have no problem switching them around. Certain ports need to be used if you want to use SPI or USB; 1 bit ports that are multiplexed with links or other ports have a 4mA drive strength whilst 1 bit ports that are not multiplexed have an 8mA drive strength. However, you can route any 1 bit port to any clock block and any clock block can be used to clock any port, so generally there's no problem swapping them around.

I haven't checked your schematic through I'm afraid.
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boeserbaer
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Postby boeserbaer » Wed Apr 21, 2010 3:08 pm

On the topic of the mixing 5 bit and 1 bit ports.

1. I am under the impression that I need to use port B only if I want to boot over xmos link? Can I boot from link C?

2. I will start a new thread on the 1 bit port issues, this design is OK, (SDRAM control via 1bit vs 4 bit) but my other board has a few SPI links for ADCs and DACs.

Thank you so much for your help.

Mike
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Woody
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Postby Woody » Wed Apr 21, 2010 3:33 pm

1. you can not boot over link C. Link B is the only external link that can be booted over. (All internal links are bootable over on an L2 device).

2. I'm sorry I'm not sure exactly what the question is here.
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Folknology
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Postby Folknology » Mon Apr 26, 2010 1:05 pm

Can I just clarify the boot/link restrictions.

Can an L1-64 boot over its link B (in 2 wire mode) connected to link A on another L1-64 which has SPI flash attached?
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Woody
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Postby Woody » Mon Apr 26, 2010 2:19 pm

Folknology wrote:Can an L1-64 boot over its link B (in 2 wire mode) connected to link A on another L1-64 which has SPI flash attached?
Yes. This is the order of events:

a) L1-64_master boots from SPI.
b) L1-64_master enables X0LA in 2w mode and sends boot code down it.
c) L1-64_slave boots from X0LB in 2w mode, connected to L1-64_master's X0LA.

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