Initial pin/port configuration/status for L series silicon

Technical discussions around xCORE processors (e.g. General Purpose (L/G), xCORE-USB, xCORE-Analog, xCORE-XA).
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Folknology
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Initial pin/port configuration/status for L series silicon

Postby Folknology » Mon Apr 26, 2010 5:30 pm

What is the default configuration and state of a 1 bit port/pin (or others for that matter) after reset.

i.e. what would be the state (and config) of any of the unused 1 bit ports (excluding SPI pins) on the L1-64 when it access the flash. Obviously I am assuming a default SPI boot process in this example.

I couldn't find this in the docs, I assume it is consistent.
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Woody
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Postby Woody » Mon Apr 26, 2010 5:36 pm

Folknology wrote:What is the default configuration and state of a 1 bit port/pin (or others for that matter) after reset.
When none of the ports connected to a pin are enabled, the internal pullups (G4) / pulldowns (L1) are active. Note that these can not be relied upon to drive out of the XCore: if you need a specific external value you should provide an external pullup/down strong enough to overcome the internal ones.

Ports are brought into use by declaring them within XC.

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