The XMOS Architecture manual states:
This seems to make sense for the G4 device, where 4 links from each core connect to the switch and 16 off-chip links enable each on-chip link to connect externally (independently) with no on-chip communication via the switch...The four XMOS Links from each XCore connect directly to an on-chip switch which provides non-blocking communication between the XCores. The switch also provides 16 off-chip XMOS Links allowing multiple XS1 chips to be combined in a system. The structure and performance of the XMOS Link connections in a system can be varied to meet the needs of applications.
Is this also true for the L1 die, or are there fewer off-chip links? Alternatively, can someone point me to the doc that details this, I'm struggling with working out which doc to read. Not interested in the package pin-out particularly, more interested in what the switch on the die is actually capable of.