L1 Switch

Technical discussions around xCORE processors (e.g. General Purpose (L/G), xCORE-USB, xCORE-Analog, xCORE-XA).
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jonathan
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L1 Switch

Postby jonathan » Fri Jun 11, 2010 7:25 pm

In which document is there information about the switch included on the L1 die? I'm unclear exactly what is supported by the on-chip switch.

The XMOS Architecture manual states:
The four XMOS Links from each XCore connect directly to an on-chip switch which provides non-blocking communication between the XCores. The switch also provides 16 off-chip XMOS Links allowing multiple XS1 chips to be combined in a system. The structure and performance of the XMOS Link connections in a system can be varied to meet the needs of applications.
This seems to make sense for the G4 device, where 4 links from each core connect to the switch and 16 off-chip links enable each on-chip link to connect externally (independently) with no on-chip communication via the switch...

Is this also true for the L1 die, or are there fewer off-chip links? Alternatively, can someone point me to the doc that details this, I'm struggling with working out which doc to read. Not interested in the package pin-out particularly, more interested in what the switch on the die is actually capable of.

Thanks.
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lilltroll
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Postby lilltroll » Fri Jun 11, 2010 9:54 pm

Probably not the most confused programmer anymore on the XCORE forum.
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jonathan
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Postby jonathan » Fri Jun 11, 2010 10:05 pm

Thanks, but not sure this covers it. This discusses the links that are bonded out onto packages, not the links that are on the die! I believe the L1 die has an XCore and a switch, and the question is whether the switch is the same switch as is on the G4 device (in terms of off-chip connectivity). I don't believe the 128TQFP version of the chip is fully-bonded out. Have I missed something in the doc? Or is it currently not documented?

Cheers.
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larry
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Postby larry » Fri Jun 11, 2010 10:19 pm

Hi Jonathan

This is not documented. Please file a support ticket or email me directly if there is anything specific you need to know.

The L1 die has 4 links. The G and L switches are fundamentally different (single-core vs four-core device).
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jonathan
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Postby jonathan » Fri Jun 11, 2010 10:35 pm

larry wrote:This is not documented.
Hmm, it is actually.

http://www.xmos.com/system/files/xsystem-xs1-L.pdf
3.3.3 XS1-L Switch Layer configuration

The core in the XS1-L is connected to the switch by four internal links, and the switch also allows connection to other chips via eight LLinks. The switch fully connects its 12 links (four internal links and eight LLinks) and can support 12 simultaneous message transfers.
This means the L1 switch has 4 links connected to the core and 8 more! So 12 in total! Cool.... shame there isn't a fully-bonded out version. :-)
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larry
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Postby larry » Sun Jun 13, 2010 7:48 am

The L1 has 8 links in total - 4 muxed with I/Os and 4 dedicated ones (not bonded out on any of the existing packages). The internal links can't talk to other chips.
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jonathan
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Postby jonathan » Sun Jun 13, 2010 12:46 pm

larry wrote:The L1 has 8 links in total - 4 muxed with I/Os and 4 dedicated ones (not bonded out on any of the existing packages). The internal links can't talk to other chips.
Yeah I was interested in what the switch could do off-chip. The 4 links connecting the XCore to the switch can presumably be used to talk to other chips by using one of the 8 external off-chip links by configuring the switch correctly.

Unless I've misunderstood something the internal L1 core can therefore use a maximum of the 4 external links (tying each internal link to an external link by configuring the switch) which means (at least) the 4 remaining dedicated off-chip links are to be used for building multi-L1 network topologies (ie purely for routing).
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Postby Woody » Mon Jun 14, 2010 9:49 am

On the XS1-L1 die there are 4 'plinks' between the XCore and the switch. There are also 8 'xmos links' which can connect to switches on other XS1-L devices. 4 of these 'xmos links' are not brought to pins but are used for internal connectivity within a chip and are only currently used on the XS1-L2 device (these are called 'dedicated' links because they are not multiplexed with ports. The other 4 'xmos links' may be brought out to pins on the XS1-L device, but not all of them are always (the 128 pin L1 device has all 4, the 64 pin L1 device has 2 of them, and the L2 has 2 from each XCore making a total of 4 - see the datasheets for more details).

Note that an XCore's 'plinks' are used when a data packet's source or destination is that XCore. Otherwise the data packets are routed around the 'xmos links'.

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