Question on MODE pins with 2 L1's

Technical discussions around xCORE processors (e.g. General Purpose (L/G), xCORE-USB, xCORE-Analog, xCORE-XA).
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Question on MODE pins with 2 L1's

Postby bearcat » Sun Jul 25, 2010 8:13 pm

Design has master / slave L1's. Master boots from flash, slave boots over XLINK. The JTAG SDO - SDI are chained. JTAG is working fine I believe to each L1.

What is the proper connections for MODE in regards to JTAG on each L1? I had configured each to boot over JTAG when plugged in. That seems to not work. Now that doesn't seem right on second thought.

Should the slave L1 always be configured to boot over XLINK, even if the JTAG is plugged in. The master L1 should change to boot to JTAG when it's plugged in. Is that correct?

On another note, the pull ups from the mode pins seem alot more than a "pull up". I guesstimate an equivalent of around 400ohms per pin. If you tie two together thats more like 200ohms pull up. That seems worthy of a note in the documentation (if this is correct) as that requires alot more to handle in a design.
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Postby bearcat » Mon Jul 26, 2010 5:23 am

Changed to always boot from XLINKS on the slave, and that threw up a timeout error in xdbg, so I guess I had it right the first time. Changed it to original boot from JTAG when plugged in.

So back to trying to get both cores to boot up. As a single node, each core boots and runs a program ok. Burnt a single core program to flash on the master, and it runs that fine as standalone.

Seeing activity on the XLINKS, but did not analyze the actual data to see what the packets are actually (that would take some time). When I stop debug, it shows:
stdcore[0] thread 0
1 wakeCore() ....
stdcore[1] thread 0
2 receiveEnd() .....
1 _Join() .....

Slowed the XLINK down to around 1MHz, verfied with a scope. Seems like it's waiting for the XLINK by the routine listed above??? Will continue looking at the XLINKS. I assume the links tie together as 0out -> 0In, 1out -> 1In, etc.
Any ideas?
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Postby larry » Mon Jul 26, 2010 11:57 am

Are you using 10.4 tools? I would suggest checking against the hardware design checklist ... -checklist.

For development via JTAG, both L1s should be set to boot from JTAG (MODE[2:3] = 00)
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Postby Corin » Mon Jul 26, 2010 5:22 pm

Hi bearcat,

The issue that you noted to do with the pull-ups is listed in the errata at the end of the datasheet.

Kind Regards,
To guarantee a logic low is seen on the following pins, the driving circuit should
present an impedance of less than 100 ohms to ground.

Pin ID Signal
19 RST_N
55, 53, 52, 51 MODE[3:0]
58 TMS
61 TCK
62 TDI
95 X0D43

Usually this is not a problem for CMOS drivers driving single inputs, however, if
one or more of these inputs are placed in parallel, additional logic buffers may be
required to guarantee correct operation.

For static inputs tied high or low, the relevant input pin should be tied directly to
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Postby bearcat » Tue Jul 27, 2010 4:42 am

Thanks, Corin. You are right I had not remembered the errata listed the mode pins also.

Hooked up a logic analyzer to the XLINK. I learned a little more about the subject. Now know how signaling works on a 2w and what a HELLO packet is. Looked Ok in general. But I was looking in the middle of the traces. Decided to probe each pin on each L1 with a scope, carefully. Sure enough had a cold solder joint on an input. Had verified with a microscope prior, guess I didn't notice one.

Good news, though. I now can learn the exciting XC language and it's capabilities.

Thanks for everyone's help.

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