Questions about buffered I/O ports in xCore-200

Technical discussions around xCORE processors (e.g. General Purpose (L/G), xCORE-USB, xCORE-Analog, xCORE-XA).
reffum
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Joined: Fri Jul 26, 2019 10:02 am

Questions about buffered I/O ports in xCore-200

Postby reffum » Fri Jul 26, 2019 10:37 am

Hello. Sorry for my English.
I have some questions about buffered I/O in xCore-200 series.
1. What does mean 32 number in the follow definition:

Code: Select all

buffered out port:32 p_dsd_clk; ?
What will happen, if I write:

Code: Select all

buffered out port p_dsd_clk; ?
2. What size has buffered I/O register?

3. If I write some value in buffered I/O port, and data begin to output. And befor the data transfer, I
write new data in port. New data will replace old data or attach to old data?
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Caleb
Experienced Member
Posts: 71
Joined: Thu Apr 04, 2013 10:14 pm

Postby Caleb » Tue Jul 30, 2019 7:29 pm

Hi,
Are you already familiar with the documentation on ports in the user guide?
https://www.xmos.com/download/xTIMEcomp ... (14.x).pdf

Sections 47.2 50.2 will be informative.

Q1:
buffered out port:32 sets "transfer width" of the buffered port to 32. A single width port is thus configured as a shift register that shifts-out the data that is written to the port register wit a statement such as p_dsd_clk <: 0xf0f0f0f0;
Since the transfer width is 32, the full 32 bits are loaded into the shift register. If the declared transfer width is declared to be a different valid number then only that many bits would be loaded into the shift register. The rate at which the data is shifted out of the port pin is determined by which clock block that has been assigned to regulate that port.

I believe that buffered out port without a :32 or :XX is default single bit depth. You should be able to find that in the document. And if you don't assign a clock source using one of the configure_out_port functions then it will operate with a default/system clock.

Q2: 32 bits
Q3: There is a FIFO for data written to the buffered output port. But if the FIFO is full and and you write new data, execution is blocked until the previously written data has been shifted out of the port. If you are writing data to a port register in a loop then the rate of execution of that loop will be regulated by the rate of the clock that the port is configured to use.

If you are configuring a port to output a clock, the ports of the 200 series devices have additional capabilities and can be configured constantly output a clock that is divided from a reference clock.
This example is from the UAC reference code base:
/* Clock bitclock clock block from master clock pin (divided) */
configure_clock_src_divide(clk_audio_bclk, p_mclk_in, (divide/2));
configure_port_clock_output(p_bclk, clk_audio_bclk);

I hope this is helpful.

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