XTAG2 link usage

Technical discussions related to any XMOS development kit or reference design. Eg XK-1A, sliceKIT, etc.
MaxFlashrom
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XTAG2 link usage

Postby MaxFlashrom » Wed Feb 23, 2011 7:10 pm

I notice on the XTAG2 1V2 schematic that it provides a a full duplex UART interface and a full-duplex 4-wire XMOS full-duplex Link interface on its XSYS connector. I have a USB Audio2 channel board which does not wire either the UART or the Link interface to its XSYS connector. I see that on the schematic for the USB audio2 Multi-channel version that XSYS link is wired to Link A on the processor. When using the ULPI interface the ports attached to pins X0D13-X0D22 and X0D2-X0D9 are unavailable. Looking at the schematics, I conclude that even though one cannot use the ports for these pins concurrently with the ULPI, one can still utilise any XMOS Links connected to the pins when their port function is not required, in this case Link A, as the MC Audio2 board seems to do? (X0D4, X0D5, X0D6,X0D7) Is this correct?

Incidentally, I note that 33R series transmission line termination resistors are shown on all four lines on the MC-A2 schematic. I would have expected only the Tx pins(X0D4, X0D5) not X0D6,X0D7 to have the 33R close to the transmitting L1/L2 chip: this is, indeed, what is shown on the XTAG2 design. As this is link A, rather than B on the target it cannot, I understand, boot the slave processor via this link without custom OTP code.

How does one exploit the functionality of the Link and UART on the XTAG2? Is this automatically done via the tools? I understand that the target can make system calls to the host via its syscall API. This works e.g. printf from my Audio2 board despite it having neither UART nor Link functionality wired via XTAG2 back to the PC host. It must do this somehow through through JTAG presently.

I am doing a schematic for a USB based design and I wish to know what benefit I might obtain from wiring up the 4 X0LA pins from my target to the host via XSYS. I will not be able to boot via Link A, but perhaps it enables one to make faster system calls? (and of course with custom software to talk faster to the XTAG2) . Booting via JTAG, as it does now, is fine for debug.

How does xrun --io use the UART and the XMOS link with an XTAG2?

I notice the Sparkfun board wires up the UART and Link B back to its XSYS2 connector. This is probably more versatile as it is then theoretically possible to boot via the link. (It doesn't use ULPI)
I note that the wiring topology for multi-chip implementation shows chips should be wired upstream via their B links. Presumably this is because the tools do a recursive program load booting each Xcore via its B Link. If it's not possible to connect upstream via B-link(for instance if using ULPI) is it possible to still perhaps boot via JTAG(chaining TDO TDI as required) and have the A link join to chips upstream for subsequent communication or is there something special in the B-links other than that the default boot loader uses them?

Regards
Max
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Folknology
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Postby Folknology » Wed Feb 23, 2011 8:53 pm

Yes LinkA can be used while using ULPI unlike the same pins as ports.

The 33R are used at the driving end to match expected line impedance, I am not familiar with the MC-A2 schematic I'm afraid.

Yes it can only boot via LinkB unless custom code is written.

The link is currently unused but I believe there are plans to use this, anyone from Xmos care to answer this point?

The UART tx/rx pins can be utilised by downloading uart code to the Xtag2 (Xmos does have an example somewhere) but this does not present it self as a virtual com over usb, rather it's a proprietary implementation. There is a command line switch to enable this but I cannot remember where that documentation is, it would be worth searching the forums perhaps.

Basically I consider the sys link and uart optional until documented otherwise.

regards
Al
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Andy
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Postby Andy » Thu Feb 24, 2011 1:31 am

MaxFlashrom wrote:I am doing a schematic for a USB based design and I wish to know what benefit I might obtain from wiring up the 4 X0LA pins from my target to the host via XSYS. I will not be able to boot via Link A, but perhaps it enables one to make faster system calls? (and of course with custom software to talk faster to the XTAG2) . Booting via JTAG, as it does now, is fine for debug.
Definitely wire up the the XLink on the XSYS... I believe there is some new functionality that uses it in a future version of the tools.
MaxFlashrom
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Joined: Fri Nov 05, 2010 2:59 pm

Postby MaxFlashrom » Thu Feb 24, 2011 7:36 pm

Thanks, guys, for the feedback.
In case you're interested, the schematics I referred to are available here:
These include updates for the required sequencing of power supplies for reliable operation.

http://www.xmos.com/support/silicon
Under "Development Kit Schematics"

Audio2 Multi-channel
https://www.xmos.com/download/accept/XM-000344-SC-1.pdf

XTAG2
http://www.xmos.com/published/xtag-2-sc ... production

Max.

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