XK1 schematic and LS1 Booting procedures

Technical discussions related to any XMOS development kit or reference design. Eg XK-1A, sliceKIT, etc.
kster59
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XK1 schematic and LS1 Booting procedures

Postby kster59 » Thu Dec 31, 2009 9:56 pm

I'd like to design my own XMOS L1 board and I'm reading through the XS1-L System Specification.

It says MODE3/MODE2 = 00 for JTAG and 11 for SPI boot.

On page 3 it says:
To boot from an SPI interface, an SPI slave device must be connected as follows.
Port Use
P1A0 SPI MISO
P1B0 SPI SS
P1C0 SPI SCLK
P1D0 SPI MOSI

However, on the XK1 schematic, it shows the SPI flash ram connected to:
XD36 P1M0 PORT_SPI_MISO
XD37 P1N0 PORT_SPI_SS
XD38 P1O0 PORT_SPI_CLK
XD39 P1P0 PORT_SPI_MOSI

1) What is the difference here and how does the XK1 able to boot from the SPI FLASH when it is connected on a different port?

2) I noticed the L1_64TQFP reference example has JP1 on Mode2/Mode3 to optionally connect to GND or otherwise left floating. On the XK1 schematic, Mode2/Mode3 are tied to TRST_N_BUF.
Does the MODE2/MODE3 pins have internal pullups and it is sufficient to tie them to TRST_N_BUF so that an XTAG2 will put it into JTAG mode when it needs to be and otherwise just boots normally from the SPI flash? It is ok to do this without the NC7WZ17 buffer or pullup resistors on Mode2/Mode3?

3) The L1_64TQFP reference design and the XTAG2 design have a power on reset chip NCP303LSN09 that holds RST_N high. The L1_64TQFP ref design also has a NC7WZ07 which holds TRST_N high at boot.

However, the XK1 doesn't have any of these chips. From my understanding the NCP303LSN09 just holds the RST_N high until the 1V has stabilized and is energy efficient.

Looking at Omer's Stamp breakout board: http://www.xcore.com/projects/xs1-l1-64-stamp-breakout

A .1uf cap + 2.2k resistor is used to provide a delay in the booting. This would save some costs and board complexity.

Has anyone tried it?
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AtomSoft
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Postby AtomSoft » Thu Dec 31, 2009 10:49 pm

Ok for the spi thing ...just to get this said i think its the way the it setup in the XN file take a look in the attached image...

Think about this $0.15USD for these "NC7WZ17"
http://www.newark.com/fairchild-semicon ... dp/38C7625

Well if you omit both ICs you save no more than $1 heh which isnt a lot for loss of great reliability.
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kster59
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Postby kster59 » Fri Jan 01, 2010 2:53 am

Usually the boot procedure is hard coded into the firmware of the chips.

There are a lot of reasons for saving parts regardless of price. Resistors/caps are cheap but still a pain to place if you are doing hand assembly. They take up board space and it's another part you need to order, etc.
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AtomSoft
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Postby AtomSoft » Fri Jan 01, 2010 8:26 am

Ok i was looking around and i think i opened every PDF related to XMOS and The XS1-L heh and dont find anything on that SPI question really...
3. Internal pull-up resistors are fitted to general purpose XCore I/O pins. Applies to both
XCore I/O and XCore Link I/Os.

5. Use for unused I/O only—the internal pull up resistor is not recommended as a
substitute for an external pull-up resistor.
The above is regarding the pin pullups. I guess it recommends you still use one...
kster59
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Postby kster59 » Fri Jan 01, 2010 9:55 pm

I do think it's odd when the manual says the SPI port "must" be P1A-P1D when it's not on the XK1.

It would make sense if the L1 firmware/OPT was changed to allow booting from a different port.

It'd be nice to make a board with as few components as possible. It seems that they should be required. Maybe I will just have to try it out and see what happens.
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Folknology
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Postby Folknology » Tue Jan 05, 2010 11:58 am

I don't quite understand the SPI port pin configuration for boot.

Is it reconfigurable via the XN file or is it fixed? Does the XK1 operate differently with regards to SPI boot, just trying to clarify things here.

regards
Al
kster59
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Postby kster59 » Wed Jan 06, 2010 1:15 am

Yes we all would like to know :)
richard
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Postby richard » Wed Jan 06, 2010 10:00 am

The boot ROM is hardcoded to use ports 1A to 1D when booting from a SPI device. To use the SPI boot mode of the boot ROM the device must be attached to these ports.

On the XK1 the OTP has been programmed with a modified version of the boot from SPI code. This code uses the ports 1M to 1P. The device boots from the OTP, executes the modified SPI boot code and then proceeds to load and execute code from a SPI device on these ports.

The ports are specified in the XN file so that xflash can use the correct ports when it writes to the flash. Additionally when xburn is used to program the secure bootloader to the OTP the SPI ports used by the secure bootloader are taken from the XN file. Therefore you can use secure boot with non standard ports (so long as they are 1bit ports).
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Folknology
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Postby Folknology » Wed Jan 06, 2010 1:36 pm

Thanks Richard that helps explain things a little

So just to clarify my understanding

The only way to change the boot SPI to use XnD36-39 (like the XK1) is by burning the OTP (via the Xn file and flash util)? It cannot be achieved otherwise?

I was hoping to relocate my SPI Boot to these pins, but that would also mean sacrificing OTP.

The reason for moving the SPI Boot is to allow more flexibility on port use, the default pins interfere with to many other functions.
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Folknology
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Postby Folknology » Wed Jan 06, 2010 3:09 pm

Hmm also an undocumented feature that leads to another possibility:
The boot mode is selected by setting pins MODE3 and MODE2:
00 do not boot; used for booting over JTAG
10 boot from ChanEnd 0, enabling LLinks C-H
11 boot from SPI
What about the missing mode:
01 boot from alternate SPI ;-)

Does the 01 boot mode actually exists or is it reserved for some hidden purpose?
just asking..

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