XC-2 Ethernet Kit:IO ports required 4 inter-processor com.?

[FBergemann]

Hi,
the hardware manual says, that for Processors 1, 2 and 3 for each there are available 24 IO Pins.
If using those for interfacing some other device, is then internal communication between the Processors still available?
May sound kind of strange, but i am playing with the idea to implement a "Rom-Port to Ethernet adapter" for Atari ST/Falcon with the XC-2. There are Hardware solutions called Ethernec, NetUSBee, Hydra.
I think it might be possible to re-implement with XC-2 - i.e. no dedicated HW for this.
One processor could handle the data line, another one the address lines and the 3rd one ROM3 sel, ROM4 sel, UDS and LDS.
- thanks!
best regards,
Frank

[Bianco]

Threads on one core can still talk to threads on another core using channels.
This still works when one core is doing the IO and the other core is doing the Ethernet.
The chip has an internal switch so the IO ports are not used to enable communication between cores.

[FBergemann]

Hi Bianco,
but why is then done a mapping for the Ports e.g. in the "Programming XC..:", Parallel Replication Example
(see my question here: https://www.xcore.com/forum/viewtopic.php?f=10&t=1394)
- thanks!
best regards,
Frank

[Bianco]

There is a port mapping because there are more logical ports than physical pins. So multiple logical ports can be multiplexed to the same physical pins. See the port mapping table in the datasheets. This makes it possible to chose the behaviour of a pin (being part of a 1-bit port, 2-bit, 4-bit etc). It has nothing to do with inter-thread communication on the same chip.

It is possible that in systems with multiple chips that ports are multiplexed with pins for the external processor bus (XMOS Link) and that if the XMOS Link is enabled, the pins cannot be used for user IO.